Parallel operation device allowing efficient parallel operational processing
View Patent ↗In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit. Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.
1. A parallel processing device, comprising plural operational blocks each comprising:
a data storage unit including a plurality of data entries each including a plurality of memory cells arranged as a memory cell array;
a plurality of arithmetic/logic processing elements, each of which couples with a corresponding entry and performs a designated operational processing on data stored in the corresponding entry;
a plurality of data transfer lines for transferring data between each of the entries and corresponding arithmetic/logic processing element; and
a plurality of data transfer circuits, arranged corresponding to said plurality of data transfer lines respectively, for transferring data between the memory cell in the corresponding entry and the corresponding arithmetic/logic processing element,
wherein each data transfer circuit transfers data stored in a first memory cell in the corresponding entry to the corresponding arithmetic/logic processing element; each arithmetic/logic processing element executes the designated operational processing for the data transferred from the first memory cell; and each data transfer circuit transfers a result data of the designated operational processing by the corresponding arithmetic/logic processing element to a second memory cell in the corresponding entry,
wherein when executing a SIMD operation instruction, the data transfer circuits select the first memory cell in the corresponding entries coupled with a same word line for an operation in the SIMD operation instruction, and
wherein when executing a MIMD operation instruction, the data transfer circuits select the first memory cell in the corresponding entries coupled with different word lines for respective operations in the MIMD operation instruction.
2. The parallel processing device according to claim 1 , wherein
each of the arithmetic/logic processing elements includes
an instruction register for storing data designating contents of operational processing,
an instruction decoder for decoding the data of the instruction register and generating a signal defining the contents of operational processing, and
a processing circuit having contents of operational processing set in accordance with an output signal of the instruction decoder.
3. The parallel processing device according to claim 2 , wherein
each of the arithmetic/logic processing elements includes
a plurality of registers for storing data used for the operational processing by the processing circuit and mask data for masking the operational processing; and
the instruction register is formed by a register, among the plurality of registers, other than the registers used when an instruction defined by the output signal of the instruction register is executed.
4. The parallel processing device according to claim 2 , wherein
the instruction decoder is formed by a combination circuit.
5. The parallel processing device according to claim 2 , wherein
the instruction decoder is formed by a multiplexer selecting an instruction from a plurality of instructions each in a code form, in accordance with the data stored in the instruction register.
6. The parallel processing device according to claim 2 , wherein
the instruction decoder includes an instruction memory storing a plurality of instructions each in a code form, and from the instruction memory, an instruction code corresponding to a designated instruction is read as a group of control signals, using the data stored in the instruction register as an address.
7. The parallel processing device according to claim 1 , wherein
in each of arithmetic/logic processing elements, either one of negation, logical product, logical sum and exclusive logical sum operations is designated individually, in accordance with the data stored in the instruction register.