Gate driving circuit and display apparatus having the same
View Patent ↗In a gate driving circuit and a display apparatus having the same, a ripple preventing part is connected to a pull-up part and a control terminal (Q-node) to reset the Q-node. The ripple preventing part includes a first ripple preventing device that resets the Q-node during a high period of the first clock within a (n−1)H period, and a second ripple preventing device that resets the Q-node during a high period of a second clock within the (n−1)H period. A back-flow preventing device is connected between a previous carry node and the second ripple preventing device to prevent an electric charge of the Q-node from flowing back to the previous carry node.
1. A gate driving circuit in which a plurality of stages are connected to each other, each stage comprising:
a pull-up part to pull up a present gate signal to a first clock during a 1H period;
a pull-down part to discharge the present gate signal to an off-voltage;
a pull-up driving part to turn on the pull-up part and turn off the pull-up part, the pull-up driving part being connected to a Q-node of the pull-up part; and
a ripple preventing part to prevent a ripple of the present gate signal and an input terminal of the pull-up driving part, wherein the ripple preventing part comprises:
a first ripple preventing device to connect the Q-node and a present output terminal during a high period of the first clock within a (n−1)H period;
a second ripple preventing device to connect the input terminal of the pull-up driving part and the Q-node during a high period of a second clock within the (n−1)H period; and
a back-flow preventing device connected between the input terminal of the pull-up driving part and the second ripple preventing device to prevent an electric charge of the Q-node from flowing back to the input terminal of the pull-up driving part.
2. The gate driving circuit of claim 1 , wherein the each stage further comprises a carry part to pull up a present carry signal to the first clock during the 1H period,
the pull-down part receives a next gate signal from a next stage and the pull-up driving part receives a previous carry signal from a previous stage through the input terminal of the pull-up driving part.
3. The gate driving circuit of claim 2 , wherein:
the first ripple preventing device comprises a first ripple preventing transistor comprising a control electrode receiving the first clock, an input electrode connected to the Q-node, and an output electrode connected to the present output terminal;
the second ripple preventing device comprises a second ripple preventing transistor comprising a control electrode receiving the second clock, an input electrode connected to the back-flow preventing device, and an output electrode connected to the Q-node; and
the back-flow preventing device comprises a back-flow preventing transistor comprising a control electrode and an input electrode commonly connected to the input terminal of the pull-up driving part and an output electrode connected to the input electrode of the second ripple preventing transistor.
4. The gate driving circuit of claim 2 , wherein:
the pull-up part comprises a pull-up transistor comprising a control electrode connected to the Q-node, an input electrode to receive the first clock, and an output electrode to output the present gate signal; and
the carry part comprises a carry transistor comprising a control electrode connected to the Q-node, an input electrode to receive the first clock, and an output electrode to output the present carry signal.
5. The gate driving circuit of claim 4 , wherein the pull-up driving part comprises:
a buffer transistor comprising a control electrode and an input electrode to commonly receive the previous carry signal, and an output electrode connected to the Q-node;
a first capacitor connected between the control electrode and the output electrode of the pull-up transistor;
a second capacitor connected between the control electrode and the output electrode of the carry transistor;
a first discharge transistor comprising a control electrode to receive the next gate signal, an input electrode to receive the off-voltage, and an output electrode connected to the output electrode of the buffer transistor; and
a second discharge transistor comprising a control electrode to receive the second clock, an input electrode to receive the off-voltage, and an output electrode connected to the output electrode of the pull-up transistor.
6. The gate driving circuit of claim 1 , wherein each stage further comprises:
a holding part to maintain the present gate signal at the off-voltage; and
an inverter to turn the holding part on or off in response to the first clock.
7. The gate driving circuit of claim 6 , wherein the holding part comprises:
a holding transistor comprising a control electrode connected to an output terminal of the inverter,
an input electrode to receive the off-voltage, and
an output electrode connected to an output terminal of the pull-up part.
8. The gate driving circuit of claim 1 , wherein the first clock has a phase opposite that of the second clock.
9. A gate driving circuit in which a plurality of stages are connected to each other, each stage comprising:
a pull-up part to pull up a present gate signal to a first clock during a 1H period;
a pull-down part to discharge the present gate signal to an off-voltage;
a pull-up driving part to turn on the pull-up part and turn off the pull-up part, the pull-up driving part being connected to a Q-node of the pull-up part; and
a ripple preventing part to prevent a ripple of the present gate signal and an input terminal of the pull-up driving part, wherein the ripple preventing part comprises:
a first ripple preventing device to connect the Q-node and a present output terminal during a high period of the first clock within a (n−1)H period; and
a holding capacitor connected between the input terminal of the pull-up part and an off-voltage terminal to reduce the ripple of the input terminal of the pull-up driving part.
10. The gate driving circuit of claim 9 , wherein the each stage further comprises a carry part to pull up a present carry signal to the first clock during the 1H period,
the pull-down part receives a next gate signal from a next stage, and the pull-up driving part receives a previous carry signal from a previous stage through the input terminal of the pull-up driving part.
11. The gate driving circuit of claim 10 , wherein the first ripple preventing device comprises a first ripple preventing transistor comprising:
a control electrode to receive the first clock,
an input electrode connected to the Q-node, and
an output electrode connected to the present output terminal.
12. The gate driving circuit of claim 10 , wherein the ripple preventing part further comprises a second ripple preventing device to connect a previous carry node and the Q-node during a high period of a second clock within the (n−1)H period.
13. The gate driving circuit of claim 12 , wherein the second ripple preventing device comprises a second ripple preventing transistor comprising:
a control electrode to receive the second clock,
an input electrode connected to the input terminal of the pull-up driving part, and
an output electrode connected to the Q-node.
14. A display apparatus, comprising:
a display part to display an image in response to a gate signal and a data signal;
a data driving circuit to apply the data signal to the display part; and
a gate driving circuit sequentially outputting the gate signal to the display part, the gate driving circuit comprising a plurality of stages connected to each other,
each stage comprising:
a pull-up part to pull up a present gate signal to a first clock during a 1H period;
a pull-down part to discharge the present gate signal to an off-voltage;
a pull-up driving part to turn on the pull-up part and turn off the pull-up part, the pull-up driving part being connected to a Q-node of the pull-up part; and
a ripple preventing part to prevent a ripple of the present gate signal and a input terminal of the pull-up driving part,
wherein the ripple preventing part comprises:
a first ripple preventing device to connect the Q-node and a present output terminal during a high period of the first clock within a (n−1)H period;
a second ripple preventing device to connect the input terminal of the pull-up driving part and the Q-node during a high period of a second clock within the (n−1)H period; and
a back-flow preventing device connected between the input terminal of the pull-up driving part and the second ripple preventing device to prevent an electric charge of the Q-node from flowing back to the input terminal of the pull-up driving part.
15. The display apparatus of claim 14 , wherein the each stage further comprises a carry part to pull up a present carry signal to the first clock during the 1H period,
the pull-down part receives a next gate signal from a next stage and the pull-up driving part receives a previous carry signal from a previous stage through the input terminal of the pull-up driving part.
16. The display apparatus of claim 15 , wherein:
the first ripple preventing device comprises a first ripple preventing transistor comprising a control electrode to receive the first clock, an input electrode connected to the Q-node, and an output electrode connected to the present output terminal;
the second ripple preventing device comprises a second ripple preventing transistor comprising a control electrode to receive the second clock, an input electrode connected to the back-flow preventing device, and an output electrode connected to the Q-node; and
the back-flow preventing device comprises a back-flow preventing transistor comprising a control electrode and an input electrode commonly connected to the input terminal of the pull-up driving part and an output electrode connected to the input electrode of the second ripple preventing transistor.
17. The display apparatus of claim 14 , wherein the display part comprises:
an array substrate comprising a plurality of gate lines to receive the gate signal, a plurality of data lines to receive the data signal, a thin film transistor to output the data signal in response to the gate signal, and a pixel electrode to receive the data signal;
an opposite substrate comprising a common electrode facing the pixel electrode, the opposite substrate being coupled with the array substrate; and
a liquid crystal layer disposed between the array substrate and the opposite substrate, wherein the pixel electrode and the common electrode control a light transmittance of the liquid crystal layer.
18. The display apparatus of claim 17 , wherein the gate driving circuit and the thin film transistor are formed on the array substrate through the same thin film process.
19. A display apparatus, comprising:
a display part to display an image in response to a gate signal and a data signal;
a data driving circuit to apply the data signal to the display part; and
a gate driving circuit to output the gate signal to the display part, in which a plurality of stages are connected to each other,
each stage of the gate driving circuit comprising:
a pull-up part to pull up a present gate signal to a first clock during a 1H period;
a pull-down part to discharge the present gate signal to an off-voltage;
a pull-up driving part to turn on the pull-up part and turn off the pull-up part, the pull-up driving part being connected to a Q-node of the pull-up part; and
a ripple preventing part to prevent a ripple of the present gate signal and an input terminal of the pull-up driving part,
wherein the ripple preventing part comprises:
a first ripple preventing device to connect the Q-node and a present output terminal during a high period of the first clock within a (n−1)H period; and
a holding capacitor connected between the input terminal of the pull-up driving part and an off-voltage terminal to reduce the ripple of the input terminal of the pull-up driving part.
20. The display apparatus of claim 19 , wherein the each stage further comprises a carry part to pull up a present carry signal to the first clock during the 1H period,
the pull-down part receives a next gate signal from a next stage, and the pull-up driving part receives a previous carry signal from a previous stage through the input terminal of the pull-up driving part.
21. The display apparatus of claim 20 , wherein the first ripple preventing device comprises a first ripple preventing transistor comprising:
a control electrode to receive the first clock,
an input electrode connected to the Q-node, and
an output electrode connected to the present output terminal.
22. The display apparatus of claim 20 , wherein the ripple preventing part further comprises a second ripple preventing device to connect the previous carry node and the Q-node during a high period of a second clock within the (n−1)H period.
23. The display apparatus of claim 22 , wherein the second ripple preventing device comprises a second ripple preventing transistor comprising:
a control electrode to receive the second clock,
an input electrode connected to the input terminal of the pull-up driving part, and
an output electrode connected to the Q-node.