IP Library Granted Patent US 7,855,531
Granted Patent B2
US 7,855,531 · App. 11/840,561 · Granted Dec 21, 2010

Charge and discharge control circuit and battery device

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Quick Facts
Patent No.
US 7,855,531
App. No.
11/840,561
Granted
Dec 21, 2010
Kind
B2
Abstract

When pulse charging is performed in an overcharge state or an overdischarge state in a charge and discharge control circuit and a battery device, a problem in that a pseudo overcurrent phenomenon occurs repeatedly to hinder normal operations of the charge and discharge control circuit and the battery device is addressed, thereby providing a safe battery device. Thus, there are provided a charge and discharge control circuit and a battery device having a structure in which charge overcurrent detection in the overcharge state and discharge overcurrent detection in the overdischarge state are invalidated.

Claims (30)

1. A charge and discharge control circuit for controlling a current limiting circuit based on a result obtained by monitoring a voltage of a battery to control charge and discharge of the battery, comprising:

an overcharge detection circuit for detecting an overcharge state of the battery by monitoring the voltage between both ends of the battery;

an overdischarge detection circuit for detecting an overdischarge state of the battery by monitoring the voltage between the both ends of the battery;

an overcurrent detection circuit for detecting one of a charge overcurrent state and a discharge overcurrent state in the battery by monitoring a voltage between both ends of the current limiting circuit;

a delay circuit for delaying a detection signal from the overcharge detection circuit, a detection signal from the overdischarge detection circuit, and a detection signal from the overcurrent detection circuit, the delay circuit being provided common to the overcharge detection circuit, the overdischarge detection circuit, and the overcurrent detection circuit; and

a logic circuit for generating a signal for controlling the current limiting circuit based on a detection signal outputted from the delay circuit,

wherein the charge and discharge control circuit invalidates detection of a charge overcurrent in the overcharge state and detection of a discharge overcurrent in the overdischarge state.

2. A charge and discharge control circuit according to claim 1 , wherein the logic circuit comprises:

charge overcurrent erroneous detection prevention means for invalidating a detection signal of the charge overcurrent in the overcharge state; and

discharge overcurrent erroneous detection prevention means for invalidating a detection signal of the discharge overcurrent in the overdischarge state.

3. A charge and discharge control circuit according to claim 1 , wherein the logic circuit comprises:

charge overcurrent erroneous detection prevention means for outputting a signal for inhibiting the detection of the charge overcurrent to the overcurrent detection circuit in the overcharge state; and

discharge overcurrent erroneous detection prevention means for outputting a signal for inhibiting the detection of the discharge overcurrent to the overcurrent detection circuit in the overdischarge state.

4. A battery device, comprising:

a battery;

a current limiting circuit for limiting one of a charge current and a discharge current of the battery; and

a charge and discharge control circuit for controlling the current limiting circuit based on a result obtained by monitoring a voltage of the battery to control charge and discharge of the battery,

wherein the charge and discharge control circuit comprises:

an overcharge detection circuit for detecting an overcharge state of the battery by monitoring the voltage between both ends of the battery;

an overdischarge detection circuit for detecting an overdischarge state of the battery by monitoring the voltage between the both ends of the battery;

an overcurrent detection circuit for detecting one of a charge overcurrent state and a discharge overcurrent state in the battery by monitoring a voltage between both ends of the current limiting circuit;

a delay circuit for delaying a detection signal from the overcharge detection circuit, a detection signal from the overdischarge detection circuit, and a detection signal from the overcurrent detection circuit, the delay circuit being provided common to the overcharge detection circuit, the overdischarge detection circuit, and the overcurrent detection circuit; and

a logic circuit for generating a signal for controlling the current limiting circuit based on a detection signal outputted from the delay circuit,

in which detection of a charge overcurrent is invalidated in the overcharge state and detection of a discharge overcurrent is invalidated in the overdischarge state.

5. A battery device according to claim 4 , wherein the logic circuit comprises:

charge overcurrent erroneous detection prevention means for invalidating a detection signal of the charge overcurrent in the overcharge state; and

discharge overcurrent erroneous detection prevention means for invalidating a detection signal of the discharge overcurrent in the overdischarge state.

6. A battery device according to claim 4 , wherein the logic circuit comprises:

charge overcurrent erroneous detection prevention means for outputting a signal for inhibiting the detection of the charge overcurrent to the overcurrent detection circuit in the overcharge state; and

discharge overcurrent erroneous detection prevention means for outputting a signal for inhibiting the detection of the discharge overcurrent to the overcurrent detection circuit in the overdischarge state.

Assignments (4)
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2007
From: ZHANG, WEI
To: SEIKO INSTRUMENTS INC.
Reel/Frame 020118/0208 →