Calibration circuit
View Patent ↗To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT 1 or ACT 2 is activated, and a calibration operation is performed for either the first replica buffer or the second replica buffer. When a second calibration command ZQCL is issued, both of the control signals ACT 1 , ACT 2 are activated and the calibration operation is performed for both the first replica buffer and the second replica buffer.
1. A calibration circuit for adjusting an impedance of an output buffer having a pull-up circuit and a pull-down circuit, the calibration circuit comprising:
a first replica buffer that has substantially the same circuit configuration as one of the pull-up circuit and the pull-down circuit; and
a second replica buffer that has substantially the same circuit configuration as the other of the pull-up circuit and the pull-down circuit, wherein
in response to a first calibration command, a calibration operation for the first replica buffer and a calibration operation for the second replica buffer are performed alternately;
in response to a second calibration command, the calibration operation is performed for the first replica buffer and then the calibration operation is performed for the second replica buffer; and
the calibration period specified by the first calibration command is shorter than the calibration period specified by the second calibration command.
2. The calibration circuit as claimed in claim 1 , wherein during a calibration period in which the calibration operation is performed for the first replica buffer, the impedance of the second replica buffer is fixed, and during a calibration period in which the calibration operation is performed for the second replica buffer, the impedance of the first replica buffer is fixed.
3. A calibration circuit for adjusting an impedance of an output buffer having a pull-up circuit and a pull-down circuit, the calibration circuit comprising:
a first replica buffer that has substantially the same circuit configuration as one of the pull-up circuit and the pull-down circuit; and
a second replica buffer that has substantially the same circuit configuration as the other of the pull-up circuit and the pull-down circuit, wherein
in response to a first calibration command, a calibration operation for the first replica buffer and a calibration operation for the second replica buffer are performed alternately, further comprising a counter for adjusting the impedances of the first and the second replica buffers, wherein the counter performs operations in synchronization with an internal clock whose frequency is lower than that of an external clock.
4. A data processing system comprising a data processor and a semiconductor memory device including an output buffer having a pull-up circuit and a pull-down circuit and a calibration circuit for adjusting an impedance of the output buffer, the calibration circuit including:
a first replica buffer that has substantially the same circuit configuration as one of the pull-up circuit and the pull-down circuit; and
a second replica buffer that has substantially the same circuit configuration as the other of the pull-up circuit and the pull-down circuit, wherein
in response to a first calibration command, a calibration operation for the first replica buffer and a calibration operation for the second replica buffer are performed alternately;
in response to a second calibration command, the calibration operation is performed for the first replica buffer and then the calibration operation is performed for the second replica buffer; and
the calibration period specified by the first calibration command is shorter than the calibration period specified by the second calibration command.
5. The calibration as claimed in claim 4 , wherein during a calibration period in which the calibration operation is performed for the first replica buffer, the impedance of the second replica buffer is fixed, and during a calibration period in which the calibration operation is performed for the second replica buffer, the impedance of the first replica buffer is fixed.
6. The calibration circuit as claimed in claim 4 , further comprising a counter for adjusting the impedances of the first and second replica buffers, wherein the counter performs operations in synchronization with an internal clock whose frequency is lower than that an of an external clock.
7. The circuit as claimed in claim 4 , wherein the calibration operation for the first replica buffer and the calibration operation for the second replica buffer are performed alternately such that each time when the first calibration command is issued, one of the calibration operation for the first replica buffer is subject to its calibration operation and the other of the calibration operation for the first replica buffer and the calibration operation for the second replica buffer is suspended from its calibration operation.