Frequency dividing systems and methods
View Patent ↗Systems and methods for producing a frequency divider output signal having a period substantially equal to three times a period of a reference input signal, comprising configuring each of three storage elements to receive a first input, a second input, and a reference input signal, and to provide a storage element output, obtaining a frequency divider output signal from at least one storage element output, and using the storage element output from each of the three storage elements as an input to another one of the three storage elements, where a phase difference between the output of the first storage element and the output of the second storage element is substantially equal to 60°.
1. A signal processing system configured to produce a divider output signal having a period substantially equal to three times a period of a reference input signal, the signal processing system comprising:
a first storage element;
a second storage element; and
a third storage element,
where each of the three storage elements is configured to receive a first input, a second input, and a reference input signal, and is configured to provide a storage element output and a frequency of each output of the three storage elements has a frequency equal to one third of a frequency of the reference input signal,
where the divider output signal is obtained from at least one storage element output, and where the divider output signal is obtained by combining only two of the three storage element outputs by adding or summing the two storage element outputs together, and
where the storage element output from each of the three storage elements is used to provide at least one input to another one of the three storage elements, where a phase difference between the output of the first storage element and the output of the second storage element is substantially equal to 60°.
2. The signal processing system of claim 1 , where each of the three storage elements comprises a plurality of transistors.
3. The signal processing system of claim 2 , where with respect to each of the three storage elements, a state of the first input is stored in the storage element at a first point in time.
4. The signal processing system of claim 3 , where a state of the storage element output at a second point in time subsequent to the first point in time is equal to the state of the first input stored in the storage element at the first point in time.
5. The signal processing system of claim 1 , where a phase difference between a third harmonic component contained in the first storage element output and a third harmonic component contained in the second storage element output is substantially 180°.
6. The signal processing system of claim 5 , where the third harmonic component contained in the first storage element output cancels out the third harmonic component contained in the second storage element output.
7. The signal processing system of claim 1 , where the divider output signal has a duty cycle substantially equal to 50%.
8. The signal processing system of claim 1 , where the reference input signal is a local oscillator signal.
9. The signal processing system of claim 1 , where the signal processing system is a frequency divider.
10. The signal processing system of claim 1 , where the signal processing system is implemented in a mobile communications device.
11. A method for producing a frequency divider output signal having a period substantially equal to three times a period of a reference input signal, comprising:
configuring each of three storage elements to receive a first input, a second input, and a reference input signal, and to provide a storage element output, wherein a frequency of each output of the three storage elements has a frequency equal to one third of a frequency of the reference input signal;
obtaining a frequency divider output signal from at least one storage element output, where the frequency divider output signal is obtained by combining only two of the three storage element outputs by adding or summing the two storage element outputs together; and
using the storage element output from each of the three storage elements as an input to another one of the three storage elements, where a phase difference between the output of the first storage element and the output of the second storage element is substantially equal to 60°.
12. The method of claim 11 , where each of the three storage elements comprises a plurality of transistors.
13. The method of claim 12 , where with respect to each of the three storage elements, a state of the first input is stored in the storage element at a first point in time.
14. The method of claim 13 , where a state of the storage element output at a second point in time subsequent to the first point in time is equal to the state of the first input stored in the storage element at the first point in time.
15. The method of claim 11 , where a phase difference between a third harmonic component contained in the first storage element output and a third harmonic component contained in the second storage element output is substantially 180°.
16. The method of claim 15 , where the third harmonic component contained in the first storage element output cancels out the third harmonic component contained in the second storage element output.
17. The method of claim 11 , where the frequency divider output signal has a duty cycle substantially equal to 50%.
18. The method of claim 11 , where the reference input signal is a local oscillator signal.