Combined micro-electro-mechanical systems device and integrated circuit on a silicon-on-insulator wafer
View Patent ↗The present invention includes a fabrication method to construct a combined MEMS device and IC on a silicon-on-insulator (SOI) wafer (MEMS-IC) using standard foundry IC processing techniques. The invention also includes the resulting MEMS-IC. Deposition layers are added to the SOI wafer and etched away to form interconnects for electronic components for the IC. In one embodiment of the present invention, standard foundry IC processing etching techniques may be used to etch away parts of the insulating layer and device layer of the SOI wafer to create fine gaps and other detailed mechanical features of the MEMS device. Finely detailed etching patterns may be added by using imprint lithography instead of using contact or optical lithography.
1. A method for fabricating a combined micro-electro-mechanical systems (MEMS) device and integrated circuit (IC) on a silicon-on-insulator (SOI) wafer comprising:
providing the SOI wafer comprising an SOI device layer over an SOI buried oxide layer;
forming at least one deposition layer over the SOI device layer;
forming at least one electronic component of the IC using the SOI device layer and the at least one deposition layer;
etching through all of the at least one deposition layer to create a MEMS device section on the SOI device layer;
after the etching through all of the at least one deposition layer, applying a hard mask to a surface of the SOI wafer;
applying imprint material over the hard mask to the MEMS device section;
imprinting a MEMS device pattern in the imprint material using a stamp; and
dry etching the MEMS device pattern through the imprint material and through the hard mask down to the SOI device layer.
2. The method of claim 1 further comprising after the dry etching the MEMS device pattern through the imprint material and through the hard mask, dry etching the MEMS device pattern through the SOI device layer down to the SOI buried oxide layer to form MEMS device gaps.
3. The method of claim 2 further comprising after the dry etching the MEMS device pattern through the SOI device layer, wet etching the SOI buried oxide layer to release a MEMS device structure.
4. The method of claim 3 further comprising:
after the forming the at least one electronic component and before the etching through all of the at least one deposition layer, applying a photo resist to a top layer of the at least one deposition layer; and
after the applying the photo resist, exposing the photo resist to form a desired pattern.
5. The method of claim 4 further comprising after the etching through all of the at least one deposition layer, removing any remaining photo resist material.
6. A method for fabricating a combined micro-electro-mechanical systems (MEMS) disk resonator and integrated circuit (IC) on a silicon-on-insulator (SOI) wafer comprising:
providing the SOI wafer comprising an SOI device layer over an SOI buried oxide layer;
forming at least one deposition layer over the SOI device layer;
forming at least one electronic component of the IC using the SOI device layer and the at least one deposition layer;
etching through all of the at least one deposition layer to create a MEMS device section on the SOI device layer;
after the etching through all of the at least one deposition layer, applying a hard mask to a surface of the SOI wafer;
applying imprint material over the hard mask to the MEMS device section;
imprinting a disk resonator pattern in the imprint material using a stamp; and
dry etching the disk resonator pattern through the imprint material and through the hard mask down to the SOI device layer.
7. The method of claim 6 further comprising after the dry etching the disk resonator pattern through the imprint material and through the hard mask, dry etching the disk resonator pattern through the SOI device layer down to the SOI buried oxide layer to form disk resonator gaps.
8. The method of claim 7 further comprising after the dry etching the disk resonator pattern through the SOI device layer, wet etching the SOI buried oxide layer to release a disk resonator structure.
9. The method of claim 8 further comprising:
after the forming the at least one electronic component and before the etching through all of the at least one deposition layer, applying a photo resist to a top layer of the at least one deposition layer; and
after the applying the photo resist, exposing the photo resist to form a desired pattern.
10. The method of claim 9 further comprising after the etching through all of the at least one deposition layer, removing any remaining photo resist material.
11. A method for fabricating a combined micro-electro-mechanical systems (MEMS) device and integrated circuit (IC) on a silicon-on-insulator (SOI) wafer comprising:
providing the SOI wafer comprising an SOI device layer over an SOI buried oxide layer;
forming at least one deposition layer over the SOI device layer;
forming at least one electronic component of the IC using the SOI device layer and the at least one deposition layer;
etching through all of the at least one deposition layer to create a MEMS device section on the SOI device layer;
after the etching through all of the at least one deposition layer, applying imprint material to the MEMS device section;
imprinting a MEMS device pattern in the imprint material using a stamp; and
dry etching the MEMS device pattern through the imprint material down to the SOI device layer.
12. The method of claim 11 further comprising after the dry etching the MEMS device pattern through the imprint material, dry etching the MEMS device pattern through the SOI device layer down to the SOI buried oxide layer to form MEMS device gaps.
13. The method of claim 12 further comprising after the dry etching the MEMS device pattern through the SOI device layer, wet etching the SOI buried oxide layer to release a MEMS device structure.
14. The method of claim 13 further comprising:
after the forming the at least one electronic component and before the etching through all of the at least one deposition layer, applying a photo resist to a top layer of the at least one deposition layer; and
after the applying the photo resist, exposing the photo resist to form a desired pattern.
15. The method of claim 14 further comprising after the etching through all of the at least one deposition layer, removing any remaining photo resist material.
16. The method of claim 11 wherein the MEMS device is a MEMS disk resonator and the MEMS device pattern is a disk resonator pattern.
17. The method of claim 16 further comprising after the dry etching the disk resonator pattern through the imprint material, dry etching the disk resonator pattern through the SOI device layer down to the SOI buried oxide layer to form disk resonator gaps.
18. The method of claim 17 further comprising after the dry etching the disk resonator pattern through the SOI device layer, wet etching the SOI buried oxide layer to release a disk resonator structure.
19. The method of claim 18 further comprising:
after the forming the at least one electronic component and before the etching through all of the at least one deposition layer, applying a photo resist to a top layer of the at least one deposition layer; and
after the applying the photo resist, exposing the photo resist to form a desired pattern.
20. The method of claim 19 further comprising after the etching through all of the at least one deposition layer, removing any remaining photo resist material.