IP Library Granted Patent US 7,734,856
Granted Patent B2
US 7,734,856 · App. 11/842,965 · Granted Jun 8, 2010

Method for operating a plurality of arbiters and arbiter system

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Quick Facts
Patent No.
US 7,734,856
App. No.
11/842,965
Granted
Jun 8, 2010
Kind
B2
Abstract

Embodiments related to arbitration are described and depicted.

Claims (26)

1. A method comprising:

operating a plurality of arbiters in a pipelined mode, wherein in the pipelined mode a request advances one stage of the pipeline per clock cycle; and

operating at least a part of the plurality of arbiters in a non-pipelined operation, wherein in the non-pipelined operation a request advances at least two stages of the pipeline per clock cycle.

2. The method according to claim 1 , wherein the pipelined mode comprises:

providing a first signal from a first arbiter to a second arbiter based on an arbitration at the first arbiter;

and wherein the non-pipelined operation comprises:

providing a second signal to the second arbiter independent of an arbitration at the first arbiter and arbitrating at the second arbiter based on the second signal.

3. The method according to claim 1 , wherein the at least part of the plurality of arbiters is operated in a non-pipelined operation when the at least part of the plurality of arbiters has been idle or had no active pipeline request in the previous clock cycle.

4. The method according to claim 1 , wherein the non-pipelined operation comprises a parallel arbitrating of a request of at least one requester of a plurality of requesters.

5. The method according to claim 1 , further comprising: storing for each of the plurality of arbiters information indicating ports granted by a respective one of the plurality of arbiters.

6. The method according to claim 1 , wherein the request advances in the non-pipelined mode all of the stages of the pipeline within one clock cycle.

7. The method according to claim 1 , wherein, when the plurality of arbiters is idle, a requester is given grant by the plurality of arbiters for data transfer to a shared resource one clock cycle after the requester has issued a request for grant to the plurality of arbiters.

8. The method according to claim 2 , wherein the second signal is provided in the pipelined and non-pipelined operation, and wherein in the pipelined operation arbitrating at the second arbiter based on the first signal is prioritized over arbitrating based on the second signal.

9. The method according to claim 2 , wherein the plurality of arbiters are arbiters of a hierarchical arbitration system, the first signal is a pipeline request signal and the second signal is a look-ahead signal and

wherein the operating in the pipelined mode comprises providing the pipeline request signal from the first arbiter to a first input port of the second arbiter based on the arbitrating among the plurality of input ports at the first arbiter, wherein the second arbiter is implemented on a higher-level stage than the first arbiter;

and wherein the non-pipelined operation comprises providing the look-ahead signal to a first input port of the second arbiter of a higher-level stage, wherein the look-ahead signal is independent of an arbitrating in the first arbiter and providing a third signal indicating a grant for the first input port based on the look-ahead signal.

10. The method according to claim 5 , further comprising providing a data path from a requester to a shared resource based on the information stored for each of the plurality of arbiters.

11. An arbiter system comprising:

a plurality of arbiters, wherein the plurality of arbiters is capable of operating in a pipelined operation, wherein in the pipelined mode a request advances one stage of the pipeline per clock cycle, and wherein at least a part of the plurality of arbiters is capable of selectively operating in a non-pipelined operation, wherein in the non-pipelined operation a request advances at least two stages of the pipeline per clock cycle.

12. The arbiter system according to claim 11 , wherein the at least part of the plurality of arbiters is operated in a non-pipelined operation when the at least part of the plurality of arbiters is in an idle state.

13. The arbiter system according to claim 11 , wherein the plurality of arbiters is configured to initiate, when the plurality of arbiters is initially idle, a data transfer for a requester one clock cycle after the requester has requested access.

14. The arbiter system according to claim 11 , wherein the plurality of arbiters form a hierarchical arbitration system.

15. The arbiter system according to claim 14 , wherein each of the plurality of arbiters is coupled to a corresponding register to store information indicating a port granted by each of the plurality of arbiters.

16. The arbiter system according to claim 15 , wherein the corresponding register is coupled to a corresponding multiplexer to provide a data path from a requester to a shared source based on information stored in each of the corresponding register.

17. The arbiter system according to claim 16 , wherein the plurality of arbiters is configured to provide in the pipelined operation a first signal from a first arbiter to a second arbiter of a next higher stage based on an arbitration at the first arbiter and wherein in the non-pipelined operation a second signal is provided to the second arbiter independent of an arbitration in the first arbiter.

18. The arbiter system according to claim 17 , wherein the second signal is further provided in the pipelined operation, and wherein arbitration based on the first signal is prioritized over arbitration based on the second signal.

Assignments (10)
SECURITY AGREEMENT Recorded Jul 9, 2021
From: MAXLINEAR, INC.; MAXLINEAR COMMUNICATIONS, LLC; EXAR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 056816/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2020
From: INTEL CORPORATION
To: MAXLINEAR, INC.
Reel/Frame 053626/0636 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2020
From: LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: INTEL CORPORATION
Reel/Frame 053259/0678 →
MERGER AND CHANGE OF NAME Recorded Jan 17, 2018
From: LANTIQ DEUTSCHLAND GMBH; LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 045085/0292 →
MERGER Recorded Dec 18, 2017
From: LANTIQ DEUTSCHLAND GMBH
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 044907/0045 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 025413/0340 AND 025406/0677 Recorded Apr 17, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 035453/0712 →
GRANT OF SECURITY INTEREST IN U.S. PATENTS Recorded Nov 29, 2010
From: LANTIQ DEUTSCHLAND GMBH
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 025406/0677 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2010
From: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
To: LANTIQ DEUTSCHLAND GMBH
Reel/Frame 024529/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2010
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
Reel/Frame 024483/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2007
From: REINIG, HELMUT; SONNTAG, SOEREN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 019928/0618 →