Power control apparatus and method thereof
A power control apparatus including an active block in which power is always maintained in an on state and an N number of power management units having a hierarchical structure where N is a natural number greater than or equal to 1. Each of the power management units controls power of at least one power domain block Power of a first power management unit of the N number of the power management units is controlled by the active block, and power of an N th power management unit of the N number of the power management units is controlled by an (N−1) th power management unit.
1. A power control apparatus comprising:
an active block in which power is maintained in a power-on state; and
an N number of power management units having a hierarchical structure where N is a natural number greater than or equal to 1,
wherein each of the power management units controls power of at least one power domain block, power of a first power management unit of the N number of the power management units is controlled by the active block, and power of an Nth power management unit of the N number of the power management units is controlled by an (N−1)th power management unit,
wherein each of the power management units comprises:
an MTCMOS controller that controls power of the at least one power domain block corresponding to each of the power management units or power of a lower power management unit of each of the power management units; and
a state machine that controls the MTCMOS controller,
wherein the state machine comprises a floating prevention circuit (FPC) temporarily storing information stored in the state machine when the state machine is even in a power-off state and outputting the stored information to the active block or a higher power management unit of the power management unit having the state machine.
2. A power control apparatus comprising:
an active block in which power is maintained in a power-on state; and
an N number of power management units having a hierarchical structure where N is a natural number greater than or equal to 1,
wherein each of the power management units controls power of at least one power domain block, power of a first power management unit of the N number of the power management units is controlled by the active block, and power of an Nth power management unit of the N number of the power management units is controlled by an (N−1)th power management unit,
wherein each of the power management units comprises:
an MTCMOS controller that controls power of the at least one power domain block corresponding to each of the power management units or power of a lower power management unit of each of the power management units; and
a state machine that controls the MTCMOS controller,
wherein the MTCMOS controller comprises a floating prevention circuit (FPC) temporarily storing information stored in the MTCMOS controller even when the MTCMOS controller is in a power-off state and outputting the stored information to a lower power management unit of the power management unit having the MTCMOS controller.
3. A power control apparatus comprising:
an active block in which power is maintained in a power-on state; and
an N number of power management units having a hierarchical structure where N is a natural number greater than or equal to 1,
wherein each of the power management units controls power of at least one power domain block, power of a first power management unit of the N number of the power management units is controlled by the active block, and power of an Nth power management unit of the N number of the power management units is controlled by an (N−1)th power management unit,
wherein each of the power management units comprises:
an MTCMOS controller that controls power of the at least one power domain block corresponding to each of the power management units or power of a lower power management unit of each of the power management units; and
a state machine that controls the MTCMOS controller,
wherein each of the power management units comprises a floating prevention circuit (FPC) temporarily storing information stored in each of the power management units when each of the power management units is even in a power-off state and outputting the stored information to the at least one power domain block controlled by each of the power management units.
4. A power control apparatus comprising:
an active block in which power is maintained in a power-on state; and
an N number of power management units having a hierarchical structure where N is a natural number greater than or equal to 1,
wherein each of the power management units controls power of at least one power domain block, power of a first power management unit of the N number of the power management units is controlled by the active block, and power of an Nth power management unit of the N number of the power management units is controlled by an (N−1)th power management unit,
wherein each of the power management units comprises:
an MTCMOS controller that controls power of the at least one power domain block corresponding to each of the power management units or power of a lower power management unit of each of the power management units; and
a state machine that controls the MTCMOS controller,
wherein each of the power management units outputs a request signal requesting information about a state of each of the at least one power domain block to each of the at least one power domain block controlled by each of the power management units, receives a response signal output from each of the at least one power domain block in response to the request signal, and outputs a control signal controlling power of each of the at least one power domain block based on the received response signal.
5. A power control apparatus comprising:
an active block in which power is maintained in a power-on state; and
an N number of power management units having a hierarchical structure where N is a natural number greater than or equal to 1,
wherein each of the power management units controls power of at least one power domain block, power of a first power management unit of the N number of the power management units is controlled by the active block, and power of an Nth power management unit of the N number of the power management units is controlled by an (N−1)th power management unit
wherein each of the power management units comprises:
an MTCMOS controller that controls power of the at least one power domain block corresponding to each of the power management units or power of a lower power management unit of each of the power management units; and
a state machine that controls the MTCMOS controller,
wherein, to wake up the at least one power domain block controlled by a lower power management unit of the power management unit having the state machine, the state machine outputs a wake-up signal to the state machine included in the lower power management unit.
6. A power control apparatus comprising:
an active block in which power is maintained in a power-on state; and
an N number of power management units having a hierarchical structure where N is a natural number greater than or equal to 1,
wherein each of the power management units controls power of at least one power domain block, power of a first power management unit of the N number of the power management units is controlled by the active block, and power of an Nth power management unit of the N number of the power management units is controlled by an (N−1)th power management unit,
wherein each of the power management units comprises:
an MTCMOS controller that controls power of the at least one power domain block corresponding to each of the power management units or power of a lower power management unit of each of the power management units; and
a state machine that controls the MTCMOS controller,
wherein, when the power management unit having the state machine enters a power-off state, the state machine outputs a power-off signal to the state machine included in a higher power management unit of the power management unit having the state machine.
7. The power control apparatus of claim 4 , wherein the state machine receives the response signal and outputs a first controller control signal to the MTCMOS controller to control the power of each of the at least one power domain block based on the received response signal.
8. The power control apparatus of claim 5 , wherein the state machine further outputs a second controller control signal to the MTCMOS controller to wake up the lower power management unit and the MTCMOS controller outputs a second control signal to wake-up the lower power management unit in response to the second controller control signal.
9. A portable terminal comprising:
a power control apparatus comprising:
an active block in which power is maintained in a power-on state; and
an N number of power management units having a hierarchical structure where N is a natural number greater than or equal to 1,
wherein each of the power management units controls power of at least one power domain block, power of a first power management unit of the N number of the power management units is controlled by the active block, and power of an N th power management unit of the N number of the power management units is controlled by an (N−1) th power management unit; and
a CPU receiving power controlled by the power control apparatus,
wherein each of the power management units comprises:
an MTCMOS controller that controls power of the at least one power domain block corresponding to each of the power management units or power of a lower power management unit of each of the power management units; and
a state machine that controls the MTCMOS controller,
wherein the state machine comprises a floating prevention circuit (FPC) that temporarily stores information stored in the state machine when the state machine is even in a power-off state and that outputs the stored information to the active block or a higher power management unit of the power management unit having the state machine.
10. The portable terminal of claim 9 , wherein the portable terminal is one of a PDA, cellular phone, media player, wireless computer peripheral, or wireless remote control.
11. A method of controlling a power control apparatus with N number of power management units having a hierarchical structure where N is a natural number greater than 1, the method comprising:
an active block in which power is always maintained in an power-on state waking-up a first power management unit to wake-up at least one first power domain block controlled by the first power management unit; and
the first power management unit waking-up a second power management unit to wake-up at least one second power domain block,
wherein the first power management unit outputs a request signal that requests information about a state of each of the at least one first power domain block to each of the at least one first power domain block controlled by the first power management unit, receives a response signal output from the at least one first power domain block in response to the request signal, and outputs a control signal that controls power of the at least one first power domain block based upon the received response signal.
12. A method of controlling a power control apparatus with N number of power management units having a hierarchical structure where N is a natural number greater than 3, the method comprising:
an N th power management unit outputting a first power-off signal to an (N−1) th power management unit when at least one N th power domain block controlled by the N th power management unit is all powered-off; and
receiving the first power-off signal, and the (N−1) th power management unit outputting a second power-off signal to an (N−2) th power management unit when an (N−1) th power control domain block is all powered-off,
wherein each of the power management units comprises:
an MTCMOS controller that controls power of the at least one power domain block corresponding to each of the power management units or power of a lower power management unit of each of the power management units, and
a state machine that controls the MTCMOS controller,
wherein the state machine comprises a floating prevention circuit (FPC) that temporarily stories information stored in the state machine when the state machine is even in a power-off state and that outputs the stored information to the active block or a higher power management unit of the power management unit having the state machine.