Microcomputer with configurable communication interfacing
View Patent ↗A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.
1. A data processing apparatus having a plurality of operation modes, comprising:
a central processing unit;
a nonvolatile memory unit comprising a plurality of erase blocks;
a first interface unit; and
a second interface unit,
wherein in a first operation mode, a first program is stored into a first erase block,
wherein in a second operation mode, the central processing unit is configured to perform a second operation for storing a second program, which is received from the first interface unit, to a second erase block,
wherein in a third operation mode, the central processing unit is configured to perform a third operation for storing a third program, which is received from the second interface unit, to the second erase block,
wherein the first program includes a write program for storing program data to a specified erase block of the nonvolatile memory unit, and
wherein the second program includes a communication program for receiving program data via the second interface unit.
2. A data processing apparatus according to claim 1 ,
wherein the first program further includes a second communication program for receiving program data via the first interface unit.
3. A data processing apparatus according to claim 2 ,
wherein in the first operation mode, the first program is written to the first erase block used by a ROM writer.
4. A data processing apparatus according to claim 3 ,
wherein the second interface unit is faster than the first interface unit.
5. A data processing apparatus according to claim 4 ,
wherein the write program can be called in the third operation mode.
6. A data processing apparatus according to claim 1 ,
wherein the second operation mode is a boot mode and the third operation mode is a user boot mode.