Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture

1. A method, in a data processing system, for transmitting data from a first processor to a second processor in a first set of processors of the data processing system, each processor in the data processing system having a switch, the method comprising:

creating a set of virtual channels in each switch;

transmitting the data from the first processor to the second processor through a path comprising a second set of processors in the data processing system; and

storing, in each processor of the second set of processors, the data in a virtual channel of a corresponding switch before transmitting the data to a next processor in a subset of processors, wherein the virtual channel of the corresponding switch in which the data is stored corresponds to a position of the processor in the path through which the data is transmitted from the first processor to the second processor, wherein a number of virtual channels created in each switch is determined based on a length of a longest indirect path in the data processing system and wherein the number of virtual channels created in each switch of the one or more switches is equal to a number of ports of a corresponding processor multiplied by a number of processors in the longest indirect path in the data processing system.

2. The method of claim 1 , wherein the number of virtual channels created to form the set of virtual channels is hardcoded in each switch.

3. The method of claim 1 , wherein a size of each virtual channel in the set of virtual channels is dynamically set by a corresponding switch.

4. The method of claim 3 , wherein the size of each virtual channel in the set of virtual channels has a predetermined static size and a dynamically adjustable additional size.

5. The method of claim 1 , wherein the switches are integrated into the processors of the data processing system.

6. A computer program product, for transmitting data from a first processor to a second processor in a first set of processors of a data processing system, each processor in the data processing system having a switch, comprising a non-transitory computer readable medium having a computer readable program, wherein the computer readable program, when executed in a computing device, causes the computing device to:

create a set of virtual channels in each switch;

transmit the data from the first processor to the second processor through a path comprising a second set of processors in the data processing system; and

store, in each processor of the second set of processors, the data in a virtual channel of a corresponding switch before transmitting the data to a next processor in a subset of processors, wherein the virtual channel of the corresponding switch in which the data is stored corresponds to a position of the processor in the path through which the data is transmitted from the first processor to the second processor, wherein a number of virtual channels created in each switch is determined based on a length of a longest indirect path in the data processing system and wherein the number of virtual channels created in each switch is equal to a number of ports of a corresponding processor multiplied by a number of processors in the longest indirect path in the data network.

7. The computer program product of claim 6 , wherein the number of virtual channels created to form the set of virtual channels is hardcoded in the switches.

8. The computer program product of claim 6 , wherein a size of each virtual channel in the set of virtual channels is dynamically set by a corresponding switch.

9. The computer program product of claim 8 , wherein the size of each virtual channel in the set of virtual channels has a predetermined static size and a dynamically adjustable additional size.

10. The computer program product of claim 6 , wherein the switches are integrated into the processors of the data processing system.

11. A data processing system, comprising:

a first set of processors, each processor having a switch, the first set of processors further comprising a first processor and a second processor; and

a set of switches, each processor having an associated switch in the set of switches, wherein logic in the switches operate to:

create a set of virtual channels in the switches;

transmit data from the first processor to the second processor through a path comprising a second set of processors in the data processing system; and

store, in each processor of the second set of processors, the data in a virtual channel of a corresponding switch before transmitting the data to a next processor in a subset of processors, wherein the virtual channel of the corresponding switch in which the data is stored corresponds to a position of the processor in the path through which the data is transmitted from the first processor to the second processor, wherein a number of virtual channels created in each switch is determined based on a length of a longest indirect path in the data processing system and wherein the number of virtual channels created in each switch is equal to a number of ports of a corresponding processor multiplied by a number of processors in the longest indirect path in the data network.

12. The data processing system of claim 11 , wherein the number of virtual channels created to form the set of virtual channels is hardcoded in the switches.

13. The data processing system of claim 11 , wherein a size of each virtual channel in the set of virtual channels is dynamically set by a corresponding switch.

14. The data processing system of claim 13 , wherein the size of each virtual channel in the set of virtual channels has a predetermined static size and a dynamically adjustable additional size.

15. The data processing system of claim 11 , wherein the switches are integrated into the first set of processors of the data processing system.