Half bridge circuit and method of operating a half bridge circuit

1. A half bridge circuit, the circuit comprising:

a first semiconductor switch having at least one control gate;

a second semiconductor switch having at least two control gates;

a first driver having an output connected to a control gate of the first semiconductor switch for selectively applying a first control voltage to the control gate of the first semiconductor switch; and,

a second driver having an output connected to a first control gate of the second semiconductor switch for selectively applying a second control voltage to said first control gate of the second semiconductor switch;

the output of the first driver being connected to a second control gate of the second semiconductor switch by a circuit arrangement such that when the first driver is operated to apply a high, positive voltage to the control gate of the first semiconductor switch, a positive voltage is applied to said second control gate of the second semiconductor switch, and such that when the first driver is operated to apply a low, zero or small voltage to the control gate of the first semiconductor switch, a negative voltage is applied to said second control gate of the second semiconductor switch.

2. A circuit according to claim 1 , wherein the circuit arrangement that connects the output of the first driver being connected to the second control gate of the second semiconductor switch contains passive components only.

3. A circuit according to claim 1 , wherein the circuit arrangement that connects the output of the first driver to the second control gate of the second semiconductor switch contains at least one diode and at least one capacitor, one side of the capacitor being connected to the output of the first driver, the other side of the capacitor being connected to the second control gate of the second semiconductor switch, the other side of the capacitor being connected via said at least one diode to a midpoint of the circuit, a high voltage terminal of the second semiconductor switch being connected to the midpoint of the circuit, whereby when the output of the first driver is high, the capacitor charges via said at least one diode so as to present a positive voltage to the second control gate of the second semiconductor switch, and when the output of the first driver is low, the capacitor presents a negative voltage to the second control gate of the second semiconductor switch.

4. A circuit according to claim 2 , wherein the circuit arrangement that connects the output of the first driver to the second control gate of the second semiconductor switch contains at least one diode and at least one capacitor, one side of the capacitor being connected to the output of the first driver, the other side of the capacitor being connected to the second control gate of the second semiconductor switch, the other side of the capacitor being connected via said at least one diode to a midpoint of the circuit, a high voltage terminal of the second semiconductor switch being connected to the midpoint of the circuit, whereby when the output of the first driver is high, the capacitor charges via said at least one diode so as to present a positive voltage to the second control gate of the second semiconductor switch, and when the output of the first driver is low, the capacitor presents a negative voltage to the second control gate of the second semiconductor switch.

5. A circuit according to claim 1 , wherein the second semiconductor switch is a dual gate inversion layer emitter transistor.

6. A circuit according to claim 2 , wherein the second semiconductor switch is a dual gate inversion layer emitter transistor.

7. A circuit according to claim 3 , wherein the second semiconductor switch is a dual gate inversion layer emitter transistor.

8. A circuit according to claim 4 , wherein the second semiconductor switch is a dual gate inversion layer emitter transistor.

9. A method of operating a half bridge circuit that has a first semiconductor switch having at least one control gate; a second semiconductor switch, the second semiconductor switch having at least two control gates; a first driver having an output connected to a control gate of the first semiconductor switch for selectively applying a first control voltage to the control gate of the first semiconductor switch; and, a second driver having an output connected to a first control gate of the second semiconductor switch for selectively applying a second control voltage to said first control gate of the second semiconductor switch; the output of the first driver being connected to a second control gate of the second semiconductor switch by a circuit arrangement; the method comprising:

operating the first driver to apply a high, positive voltage to the control gate of the first semiconductor switch, whereby a positive voltage is applied to said second control gate of the second semiconductor switch, and operating the first driver to apply a low, zero or small voltage to the control gate of the first semiconductor switch, whereby a negative voltage is applied to said second control gate of the second semiconductor switch.

10. A method according to claim 9 , wherein the circuit arrangement that connects the output of the first driver being connected to the second control gate of the second semiconductor switch contains passive components only.

11. A method according to claim 9 , wherein the circuit arrangement that connects the output of the first driver to the second control gate of the second semiconductor switch contains at least one diode and at least one capacitor, one side of the capacitor being connected to the output of the first driver, the other side of the capacitor being connected to the second control gate of the second semiconductor switch, the other side of the capacitor being connected via said at least one diode to a midpoint of the circuit, a high voltage terminal of the second semiconductor switch being connected to the midpoint of the circuit, whereby when the output of the first driver is high, the capacitor charges via said at least one diode so as to present a positive voltage to the second control gate of the second semiconductor switch, and when the output of the first driver is low, the capacitor presents a negative voltage to the second control gate of the second semiconductor switch.

12. A method according to claim 10 , wherein the circuit arrangement that connects the output of the first driver to the second control gate of the second semiconductor switch contains at least one diode and at least one capacitor, one side of the capacitor being connected to the output of the first driver, the other side of the capacitor being connected to the second control gate of the second semiconductor switch, the other side of the capacitor being connected via said at least one diode to a midpoint of the circuit, a high voltage terminal of the second semiconductor switch being connected to the midpoint of the circuit, whereby when the output of the first driver is high, the capacitor charges via said at least one diode so as to present a positive voltage to the second control gate of the second semiconductor switch, and when the output of the first driver is low, the capacitor presents a negative voltage to the second control gate of the second semiconductor switch.

13. A method according to claim 9 , wherein the second semiconductor switch is a dual gate inversion layer emitter transistor.

14. A method according to claim 10 , wherein the second semiconductor switch is a dual gate inversion layer emitter transistor.

15. A method according to claim 11 , wherein the second semiconductor switch is a dual gate inversion layer emitter transistor.

16. A method according to claim 12 , wherein the second semiconductor switch is a dual gate inversion layer emitter transistor.