Framebuffer Sharing for Video Processing
An integrated circuit chip configured to be coupled to a single shared memory including, in combination, a memory access module, at least one video signal processing module, and a frame rate converter, wherein the memory access module is configured to coordinate access to the single shared memory by the at least one video signal processing module and the frame rate converter.
1 . An integrated circuit chip configured to be coupled to a single shared memory comprising, in combination:
a memory access module;
at least one video signal processing module; and
a frame rate converter;
wherein the memory access module is configured to coordinate access to the single shared memory by the at least one video signal processing module and the frame rate converter.
2 . The chip of claim 1 wherein the at least one video signal processing module and the frame rater converter are configured to share algorithm information.
3 . The chip of claim 1 wherein the at least one video signal processing module is configured to store intermediate results in the single shared memory and the frame rater converter is configured to further process the intermediate results using the single shared memory.
4 . The chip of claim 1 wherein the at least one video signal processing module comprises a video decoder module.
5 . The chip of claim 1 wherein the at least one video signal processing module comprises a deinterlacer.
6 . The chip of claim 1 wherein the at least one video signal processing module comprises a scaler.
7 . A digital television receiver comprising:
a memory;
a single integrated circuit chip comprising, in combination:
a memory access module;
at least one video signal processing module; and
a frame rate converter;
wherein the memory access module is configured to coordinate access to the memory by the at least one video signal processing module and the frame rate converter.
8 . The receiver of claim 7 wherein the at least one video signal processing module and the frame rate converter are configured to share algorithm information.
9 . The receiver of claim 7 wherein the at least one video signal processing module is configured to store intermediate results in the memory and the frame rate converter is configured to further process the intermediate results using the memory.
10 . The receiver of claim 7 wherein the at least one video signal processing module comprises a video decoder module.
11 . The receiver of claim 7 wherein the at least one video signal processing module comprises a deinterlacer.
12 . The receiver of claim 7 wherein the at least one video signal processing module comprises a scaler.
13 . A method of processing video signals in a receiver, the method comprising:
accessing a single memory from a single integrated circuit chip for use in processing video signals including frame rate conversion of the signals; and
coordinating access to the single memory for frame rate conversion of the video signals and at least one of decoding, deinterlacing, and scaling the video signals.
14 . The method of claim 13 further comprising processing the video signals using a single algorithm to perform at least a portion of multiple ones of the decoding, deinterlacing, scaling, and frame rate converting.
15 . The method of claim 13 wherein the deinterlacing comprises storing intermediate results to the single memory and the frame rate converting comprises using the intermediate results.
16 . The method of claim 13 wherein the decoding comprises storing intermediate results to the single memory and the frame rate converting comprises using the intermediate results.