Thin film array panel
View Patent ↗A gate line is formed on a substrate, and a gate insulating layer is formed thereon. A data line is formed on the gate insulating layer, and a passivation layer is formed on the data line. The passivation layer has an opening exposing the gate insulating layer. A pixel electrode is formed on the passivation layer and it overlaps the data line and the passivation layer.
1. A thin film array panel comprising:
a gate line formed on a substrate;
a first insulating layer on the gate line;
a data line formed on the first insulating layer;
a second insulating layer formed on the data line and having an opening;
a pixel electrode formed on the first insulating layer and overlapping the data line and the second insulating layer; and
a third insulating layer disposed between the pixel electrode and the first insulating layer,
wherein a center portion of the pixel electrode is formed on the third insulating layer and an edge portion of the pixel electrode overlaps a lateral surface of the second insulating layer,
wherein the center portion of the pixel electrode is in direct contact with the third insulating layer,
wherein a bottom surface of the second insulating layer is in direct contact only with the third insulating layer, and
wherein the second insulating layer has a top surface and the pixel electrode does not overlap the top surface of the second insulating layer.
2. The thin film array panel of claim 1 , wherein the second insulating layer has an inclined lateral surface.
3. The thin film array panel of claim 2 , wherein the pixel electrode overlaps the lateral surface of the second insulating layer.
4. The thin film array panel of claim 3 , wherein the lateral surface of the second insulating layer has an inclination angle of about 13-40 degrees.
5. The thin film array panel of claim 1 , wherein the second insulating layer has a dielectric constant smaller than about 4.0.
6. The thin film array panel of claim 5 , wherein the second insulating layer comprises an acrylic organic material.
7. The thin film array panel of claim 1 , wherein the third insulating layer comprises inorganic material.
8. The thin film array panel of claim 7 , wherein the third insulating layer comprises silicon nitride.
9. The thin film array panel of claim 1 , wherein the second insulating layer covers the gate line.
10. The thin film array panel of claim 1 , further comprising a thin film transistor connected to the gate line, the data line, and the pixel electrode.
11. The thin film array panel of claim 1 , further comprising a light blocking film disposed between the data line and the pixel electrode.
12. The thin film array panel of claim 1 , wherein a light blocking film is formed under the first insulating layer.