Programmable Processor Architecture
One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
1 . A high performance processor comprising:
at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value and including,
at least one control block;
macro function block having,
a Galois Field multiply accumulate (MAC) block;
a special ALU;
a combiner block;
an interleaver block; and
a viterbi block.
2 . A high performance processor, as recited in claim 1 , further including a store unit block having a first store buffer and a second store buffer coupled to the macro function block through a macro function bus, and further having a load unit block including a first load buffer and a second load buffer, wherein the first and second store buffers and the first and second load buffers cause double buffering effects to reduce “stalling” resulting from simultaneous access of the store unit block and the load unit block.
3 . A high performance processor as recited in claim 1 , further including a load/store Macro Functional Units (MFU) block, and a vector X MFU for rearranging vector data.
4 . A high performance processor as recited in claim 3 , wherein the vector X MFU block is operative to generate vector store masks for vector stores to memory.
5 . A high performance processor comprising:
at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value and including,
a control block;
a load/store Macro Functional Units (MFU) block;
a scalar arithmetic logic unit (ALU);
a vector X MFU for rearranging vector data; and
a vector ALU.
6 . A high performance processor, as recited in claim 5 , further including a store unit block having a first store buffer and a second store buffer coupled to the MFU block through a macro function bus, and further having a load unit block including a first load buffer and a second load buffer, wherein the first and second store buffers and the first and second load buffers cause double buffering effects to reduce “stalling” resulting from simultaneous access of the store unit block and the load unit block.
7 . A high performance processor as recited in claim 5 , wherein the vector X MFU block is operative to generate vector store masks for vector stores to memory.