IP Library Granted Patent US 7,750,426
Granted Patent B2
US 7,750,426 · App. 11/849,565 · Granted Jul 6, 2010

Junction barrier Schottky diode with dual silicides

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Quick Facts
Patent No.
US 7,750,426
App. No.
11/849,565
Granted
Jul 6, 2010
Kind
B2
Abstract

An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

Claims (13)

1. An integrated circuit including a junction barrier Schottky diode, the diode comprising:

an N-type silicon well having surface;

a P-type anode region in the surface of the well;

a portion of the surface of the well horizontally abutting the anode region being an n-type Schottky region;

a first silicide layer on the Schottky region and an adjoining portion of the anode region, the first silicide layer forming a Schottky barrier with the Schottky region;

a second silicide layer of a different material than the first silicide layer on the anode region; and

an ohmic contact to the second silicide layer on the anode region, and an ohmic contact to the well,

wherein the first and second silicide layers are spaced from each other on the surface.

2. The integrated circuit of claim 1 , wherein the well includes an N-type cathode contact region in the surface having a higher impurity concentration than the Schottky region's impurity concentration, and the ohmic contact to the well is to the cathode contact region.

3. The integrated circuit of claim 2 , wherein the well includes an N-type buried layer having a higher impurity concentration than the well's impurity concentration and the n-type cathode contact region extends from the surface to buried layer.

4. The integrated circuit of claim 2 , wherein a portion of the second silicide layer is on a portion of the cathode contact region and the ohmic contact to the well is to the portion of the second silicide layer on the cathode contact region.

5. The integrated circuit according to claim 1 , wherein the first silicide layer is Cobalt silicide and the second silicide layer is a Titanium silicide.

6. The integrated circuit according to claim 1 , wherein the first silicide layer is Titanium silicide and the second silicide layer is a Platinum silicide.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF ASSIGNEE PREVIOUSLY RECORDED ON REEL 019777 FRAME 0942. ASSIGNOR(S) HEREBY CONFIRMS THE NAME OF ASSIGNEE WAS RECORDED INCORRECTLY AS INTERSIL AMERICAS, INC. AND SHOULD HAVE BEEN RECORDED AS INTERSIL AMERICAS INC.. Recorded Sep 29, 2014
From: GIRDHAR, DEV ALOK; CHURCH, MICHAEL DAVID; KALNITSKY, ALEXANDER
To: INTERSIL AMERICAS INC.
Reel/Frame 033845/0393 →
CHANGE OF NAME Recorded Sep 29, 2014
From: INTERSIL AMERICAS INC.
To: INTERSIL AMERICAS LLC
Reel/Frame 033845/0413 →
SECURITY AGREEMENT Recorded May 4, 2010
From: INTERSIL CORPORATION; TECHWELL, INC.; INTERSIL COMMUNICATIONS, INC.; QUELLAN, INC.; ZILKER LABS, INC.; KENET, INC.; INTERSIL AMERICAS INC.; ELANTEC SEMICONDUCTOR, INC.; D2AUDIO CORPORATION; PLANET ATE, INC.
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 024329/0411 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2007
From: GIRDHAR, DEV ALOK; CHURCH, MICHAEL DAVID; KALNITSKY, ALEXANDER
To: INTERSIL AMERICAS, INC.
Reel/Frame 019777/0942 →