Method of fabricating flash memory device with increased coupling ratio
View Patent ↗A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate; forming a photoresist as a mask on the first insulation film, and performing an etching process using the photoresist as the mask; forming a hard mask by depositing a second insulation film for prevention of oxidation on the semiconductor substrate; forming an STI by using the hard mask; oxidizing sidewalls of the STI and gap-filling the STI; forming a floating gate by removing the second insulation film remaining as the hard mask; and sequentially forming an ONO film and a control gate on the floating gate.
1. A method of fabricating a flash memory device comprising:
sequentially forming a tunnel oxide film, a polysilicon film and a first insulation film for a floating gate on an active area of a semiconductor substrate;
forming a photoresist as a mask on the first insulation film;
performing an etching process using the photoresist as the mask;
forming a hard mask for prevention of oxidation on the semiconductor substrate;
forming an STI by using the hard mask;
oxidizing sidewalls of the STI and gap-filling the STI;
forming the floating gate by removing the hard mask; and
sequentially forming an ONO film and control gate on the floating gate, wherein the floating gate is larger than the tunnel oxide film in size of area, to obtain a coupling ratio between the floating gate and the control gate.
2. The method of claim 1 , wherein forming the hard mask includes depositing a second insulation film on the semiconductor substrate.
3. The method of claim 2 , wherein the second insulation film prevents oxidation.
4. The method of claim 2 , wherein removing the hard mask includes removing the second insulation film remaining as the hard mask.
5. The method of claim 2 , wherein the first and second insulation films are formed of oxide films of SiO 2 .
6. The method of claim 2 , wherein the first and second insulation films are formed of nitride films of SiN.
7. The method of claim 1 , wherein the first insulation film and the polysilicon film are etched by using the photoresist as the mask.
8. The method of claim 1 , wherein the tunnel oxide film has a thickness between approximately 30 Å and approximately 300 Å.
9. The method of claim 8 , wherein the tunnel oxide film is grown.
10. The method of claim 8 , wherein the tunnel oxide film is deposited.
11. The method of claim 1 , wherein the sidewalls of the STI are oxidized in an oxide-oxidization method.
12. The method of claim 1 , wherein the sidewalls of the STI are oxidized in an oxide-oxidization method, and then the STI is gap-filled to prevent forming voids therein.
13. The method of claim 1 , wherein the flash memory device has an ETOX (EPROM Thin Oxide) cell structure.