Register error correction of speculative data in an out-of-order processor
In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.
1. A processor comprising:
a first register file configured to store speculative register state, the first register file protected by a first error protection scheme;
a second register file configured to store committed register state, the second register file protected by a second error protection scheme;
a check circuit coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed, wherein the check circuit is configured to detect an error in the value responsive to the value and the check bits;
a control unit coupled to the check circuit and configured to cause reexecution of the first instruction responsive to the error detected by the check circuit; and
a second check circuit coupled to receive a source operand read from the first register file for a second instruction and corresponding one or more check bits, wherein the second check circuit is configured to detect a source error in the source operand, and wherein the control unit is coupled to the second check circuit and is configured to cause reexecution of a second instruction responsive to the source error.
2. The processor as recited in claim 1 wherein the control unit is configured to cause reexecution responsive to selecting the second instruction to be committed.
3. The processor as recited in claim 1 further comprising a third check circuit coupled to receive a second source operand read from the second register file for a third instruction and corresponding one or more check bits, wherein the third check circuit is configured to detect a second source error in the second source operand, and wherein the control unit is coupled to the third check circuit and is configured to trap the third instruction responsive to the second source error.
4. The processor as recited in claim 1 wherein the first error protection scheme comprises parity.
5. The processor as recited in claim 4 wherein a single parity bit is implemented per register value in the first register file.
6. The processor as recited in claim 4 wherein the second error protection scheme comprises a Hamming code.
7. The processor as recited in claim 1 further comprising a fetch unit configured to fetch instructions for execution, wherein the control unit is configured to cause reexecution of the first instruction by signalling the fetch unit to refetch the first instruction.
8. The processor as recited in claim 1 further comprising an error code generation circuit configured to generate check bits for storage in the second register file responsive to the value, and wherein the value and the check bits are written to the second register file if no error is detected.
9. The processor as recited in claim 1 wherein one or more check bits according to the first error protection scheme are generated during execution of the first instruction and are stored in the first register file with the value.
10. A processor comprising:
a first register file configured to store speculative register state, the first register file protected by parity;
a second register file configured to store committed register state, the second register file protected by a second error protection scheme that is more robust than parity;
a check circuit coupled to receive a value and corresponding parity read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed, wherein the check circuit is configured to detect an error in the value responsive to the value and corresponding parity;
an error code generation circuit coupled to receive the value read from the first register file to be committed to the second register file in response to the processor selecting the first instruction to be committed, wherein the error code generation circuit is configured to generate a second one or more check bits for storage in the second register file responsive to the value, and wherein the value and the second one or more check bits are written to the second register file responsive to a lack of error being detected by the check circuit; and
a control unit coupled to the check circuit and configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.
11. The processor as recited in claim 10 further comprising a fetch unit configured to fetch instructions for execution, wherein the control unit is configured to cause reexecution of the first instruction by signalling the fetch unit to refetch the first instruction.
12. A processor comprising:
a first register file configured to store speculative register state, the first register file protected by a first error protection scheme;
a second register file configured to store committed register state, the second register file protected by a second error protection scheme;
a check circuit coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed, wherein the check circuit is configured to detect an error in the value responsive to the value and the check bits;
an error code generation circuit coupled to receive the value read from the first register file to be committed to the second register file in response to the processor selecting the first instruction to be committed, wherein the error code generation circuit is configured to generate a second one or more check bits for storage in the second register file responsive to the value, and wherein the value and the second one or more check bits are written to the second register file responsive to a lack of error being detected by the check circuit; and
a control unit coupled to the check circuit and configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.
13. The processor as recited in claim 12 further comprising a second check circuit coupled to receive a source operand read from the first register file for a second instruction and corresponding one or more check bits, wherein the second check circuit is configured to detect a source error in the source operand, and wherein the control unit is coupled to the second check circuit and is configured to cause reexecution of a second instruction responsive to the source error.
14. The processor as recited in claim 13 wherein the control unit is configured to cause reexecution responsive to selecting the second instruction to be committed.
15. The processor as recited in claim 13 further comprising a third check circuit coupled to receive a second source operand read from the second register file for a third instruction and corresponding one or more check bits, wherein the third check circuit is configured to detect a second source error in the second source operand, and wherein the control unit is coupled to the third check circuit and is configured to trap the third instruction responsive to the second source error.
16. The processor as recited in claim 12 wherein the first error protection scheme comprises parity.
17. The processor as recited in claim 16 wherein a single parity bit is implemented per register value in the first register file.
18. The processor as recited in claim 16 wherein the second error protection scheme comprises a Hamming code.
19. The processor as recited in claim 12 further comprising a fetch unit configured to fetch instructions for execution, wherein the control unit is configured to cause reexecution of the first instruction by signalling the fetch unit to refetch the first instruction.