SYSTEMS AND METHODS FOR BALL GRID ARRAY (BGA) ESCAPE ROUTING
A ball grid array (BGA) package and its corresponding printed circuit board incorporate an improved escape routing scheme. The substrate includes a plurality of conductive pads having a periphery defined by a predetermined edge pattern forming routing channels therebetween. A plurality of signal lines connected to a subset of the conductive pads extends beyond the periphery through the routing channels. The predetermined pattern may, for example, be a right triangle repeating with a periodicity along the periphery of the array, wherein the right triangle has a first side defined by a number of rows in the array, and a second side, perpendicular to the first, defined by a number of layers in the array.
1 . A substrate of the type configured to connect to a ball grid array package having an array pattern, the substrate comprising:
a plurality of conductive pads disposed in said array pattern, the array pattern having a periphery defined by a predetermined edge pattern forming routing channels therebetween; and
a plurality of signal lines connected to a subset of the conductive pads and extending beyond the periphery through the routing channels.
2 . The substrate of claim 1 , wherein the predetermined edge pattern is a right triangle.
3 . The substrate of claim 2 , wherein the predetermined edge pattern is a right triangle having a first side defined by a number of rows and a second side defined by a number of layers, wherein the first side is substantially perpendicular to the second side.
4 . The substrate of claim 3 , wherein the predetermined edge pattern repeats with a periodicity R along the periphery, and wherein R is the number of rows defining the first side of the right triangle.
5 . The substrate of claim 4 , wherein the number of layers defining the second side of the right triangle is equal to R.
6 . The substrate of claim 5 , wherein R is between 2 and 8 , inclusive.
7 . The substrate of claim 4 , wherein the array pattern is characterized by an escape efficiency, and wherein the escape efficiency is greater than about 75% for values of R greater than 2.
8 . A method of forming a substrate configured to connect to a ball grid array package having an array pattern, comprising:
forming a plurality of conductive pads in accordance with the array pattern such that the array pattern has a periphery defined by a predetermined edge pattern that defines routing channels therebetween; and
forming a plurality of signal lines connected to a subset of the conductive pads and extending beyond the periphery through the routing channels.
9 . The method of claim 8 , wherein forming the plurality of conductive pads includes forming the predetermined edge pattern as a right triangle.
10 . The method of claim 9 , wherein the predetermined edge pattern is a right triangle having a first side defined by a number of rows and a second side defined by a number of layers, wherein the first side is substantially perpendicular to the second side.
11 . The method of claim 10 , wherein the predetermined edge pattern repeats with a periodicity R along the periphery, and wherein R is the number of rows defining the first side of the right triangle.
12 . The method of claim 11 , wherein the number of layers defining the second side of the right triangle is equal to R.
13 . The method of claim 12 , wherein R is between 2 and 8 , inclusive.
14 . The method of claim 11 , wherein the array pattern is characterized by an escape efficiency, and wherein the escape efficiency is greater than about 75% for values of R greater than 2.
15 . A ball grid array package comprising a plurality of solder balls configured in an array pattern, the array pattern having a periphery defined by a predetermined repeating edge pattern.
16 . The package of claim 15 , wherein the predetermined edge pattern is a right triangle that repeats with a periodicity R along the periphery, and wherein R is the number layers within the array pattern defining a side of the right triangle.
17 . The package of claim 16 , wherein R is between 2 and 8 , inclusive.
18 . The package of claim 16 , wherein the array pattern is characterized by an escape efficiency, and wherein the escape efficiency is greater than about 75% for values of R greater than 2.
19 . The package of claim 16 , wherein the array pattern has a pitch of between about 38 and 42 mils.
20 . The package of claim 16 , wherein a subset of the solder balls are associated with input/output pins, and wherein the subset is located within a depth R along the periphery of the array.