Granted Patent B2

US 7,889,164 · App. 11/851,927 · Granted Feb 15, 2011

Abstract

Claims (41)

1. A mobile terminal device comprising:

a first casing half; and

a second casing half foldably coupled to said first casing half via a hinge member,

wherein said first casing half comprises a host device,

wherein said second casing half comprises: a liquid crystal display drive controller interfaced with said host device via a plurality of signal lines; a liquid crystal display whose display operation is controlled by said liquid crystal display drive controller; a sub liquid crystal display drive controller coupled to said liquid crystal display drive controller; and a sub liquid crystal display whose display operation is controlled by said sub liquid crystal display drive controller,

wherein said signal lines go through said hinge member,

wherein said liquid crystal display drive controller comprises a semiconductor integrated circuit device which includes: external terminals for host interface; a host interface circuit coupled to said external terminals for host interface; a display drive circuit coupled to said host interface circuit; and external terminals for display drive coupled to said display drive circuit,

wherein said host interface circuit comprises: a first serial interface circuit for serial data input and output in a differential manner; a parallel interface circuit; and other interface circuits,

wherein an interface circuit for use as an interface with a host device is selected according to a host interface mode setting,

wherein said host interface circuit, when said first serial interface circuit is selected for use as the interface with said host device, outputs in parallel information for said sub liquid crystal display drive controller, input from said host device via said first serial interface circuit, from said parallel interface circuit to said sub liquid crystal display drive controller and generates interface control signals for the parallel output, and

wherein external terminals for host interface assigned to said other interface circuits are used for double duty to output said generated interface control signals to said sub liquid crystal display drive controller.

2. The mobile terminal device according to claim 1 ,

wherein said other interface circuits include a second serial interface circuit for clock-synchronized serial interfacing at a lower speed than said first serial interface circuit, and

wherein a serial data output terminal assigned to said second serial interface circuit is one external terminal for host interface which is used for double duty to output one of said interface control signals.

3. The mobile terminal device according to claim 2 , further comprising:

a display data memory capable to be used as a frame buffer of display data which is supplied to said drive circuit,

wherein said other interface circuits include a bitmap input control interface circuit for inputting timing control signals for rendering image data which is input via said parallel interface circuit into the frame buffer,

wherein, as said timing control signals, a data enable signal which indicates that valid data is present, a horizontal synchronization signal, a vertical synchronization signal, and a dot clock which specifies timing for taking in data are input, and

wherein an input terminal for said input data enable signal and an input terminal for the horizontal synchronization signal are the remaining external terminals for host interface which are used for double duty to output the remaining ones of said interface control signals.

4. The mobile terminal device according to claim 3 , wherein said interface control signals are a chip select signal which instructs to select said sub liquid crystal display drive controller, a write signal to instruct said sub liquid crystal display drive controller to write data, and a register select signal for selecting a register to which to write data.

5. The mobile terminal device according to claim 4 , wherein said external terminals for host interface are arranged along one of two opposite longitudinal edges of the semiconductor chip and said external terminals for display drive are arranged along the other one of the two opposite longitudinal edges of the semiconductor chip, and the external terminals for host interface assigned to said first serial interface circuit are disposed, spaced apart from the external terminals for host interface assigned to said parallel interface circuit and other interface circuits, with external terminals for power supply and ground lines being interposed.

6. A semiconductor integrated circuit device comprising:

external terminals for host interface;

a host interface circuit coupled to said external terminals for host interface;

a display drive circuit coupled to said host interface circuit; and

external terminals for display drive coupled to said display drive circuit,

wherein said host interface circuit comprises a first serial interface circuit for serial data input and output in a differential manner, a parallel interface circuit, and other interface circuits,

wherein an interface circuit for use as an interface with a host device is selected according to a host interface mode setting,

wherein said host interface circuit, when said first serial interface circuit is selected for use as the interface with said host device, outputs in parallel predetermined information input from said host device via said first serial interface circuit from said parallel interface circuit to outside and generates interface control signals for the parallel output, and

wherein external terminals for host interface assigned to said other interface circuits are used for double duty to output said generated interface control signals.

7. The semiconductor integrated circuit device according to claim 6 ,

wherein said other interface circuits include a second serial interface circuit for clock-synchronized serial interfacing at a lower speed than said first serial interface circuit, and

wherein a serial data output terminal assigned to said second serial interface circuit is one external terminal for host interface which is used for double duty to output one of said interface control signals.

8. The semiconductor integrated circuit device according to claim 7 , further comprising:

a display data memory capable to be used as a frame buffer of display data which is supplied to said drive circuit,

wherein said other interface circuits include a bitmap input control interface circuit for inputting timing control signals for rendering image data which is input via said parallel interface circuit into the frame buffer,

wherein, as said timing control signals, a data enable signal which indicates that valid data is present, a horizontal synchronization signal, a vertical synchronization signal, and a dot clock which specifies timing for taking in data are input, and

wherein an input terminal for said input data enable signal and an input terminal for the horizontal synchronization signal are the remaining external terminals for host interface which are used for double duty to output the remaining ones of said interface control signals.

9. The semiconductor integrated circuit device according to claim 8 , wherein said predetermined information is information for display control to be supplied to another semiconductor integrated circuit device for display control.

10. The semiconductor integrated circuit device according to claim 9 , wherein said interface control signals are a chip select signal, a write signal, and a register select signal.

11. The semiconductor integrated circuit device according to claim 10 , wherein said external terminals for host interface are arranged along one of two opposite longitudinal edges of the semiconductor chip and said external terminals for display drive are arranged along the other one of the two opposite longitudinal edges of the semiconductor chip, and the external terminals for host interface assigned to said first serial interface circuit are disposed, spaced apart from the external terminals for host interface assigned to said parallel interface circuit and other interface circuits, with external terminals for power supply and ground lines being interposed.

Assignments (9)