Delay lock loop delay adjusting method and apparatus
View Patent ↗Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is then changed until a preferred delay value, resulting in synchronization, is found. In various embodiments, used of the initial delay value increases the speed, reliability or other beneficial features of the synchronization.
1. A method for adjusting a delay lock loop comprising:
sending a test signal to a delay circuit and receiving a response signal responsive to the test signal;
receiving a first value from a counter when the test signal is sent;
receiving a second value from the counter when the response signal is received;
determining a delay time by subtracting the first value from the second value;
changing the delay time to provide a synchronization between a system clock signal associated with a processor and a device clock signal associated with a device coupled to the processor.
2. The system of claim 1 , wherein the synchronization includes minimizing a phase difference between an edge of the clock signal and an edge of the device signal.
3. The system of claim 1 , wherein changing the delay time comprises incrementing the delay time by a predetermined value.
4. The system of claim 1 , wherein changing the delay time comprises decrementing the delay time by a predetermined value.
5. The system of claim 1 , wherein changing the delay time comprises changing the delay time by an amount smaller than the initial value of the delay time.
6. The system of claim 1 , further comprising communicating the delay time to a programmable delay circuit.
7. A method comprising:
sending a test signal to a delay circuit;
receiving a response signal from the delay circuit responsive to the test signal;
determining a delay value according to a propagation time between sending the test signal and receiving the response signal;
determining a delay time between a clock signal and one or more device signals using the delay value;
communicating the delay value to a delay lock loop configured to provide a preferred delay time between a clock signal and one or more device signals using the delay value; and
changing the delay time to provide the preferred delay time between the clock signal and the one or more device signals.
8. The method of claim 7 , wherein the step of changing the delay time further includes using a delay adjustment value.
9. The system of claim 7 , wherein the step of changing the delay time further includes decreasing the delay time.
10. The system of claim 7 , wherein the step of changing the delay time further includes increasing the delay time.
11. The system of claim 7 , wherein a propagation time of the test signal is responsive to temperature.
12. The system of claim 7 , wherein a propagation time of the test signal is responsive to a supply voltage.
13. A method for adjusting a delay lock loop comprising:
sending a test signal to a delay circuit and receiving a response signal responsive to the test signal;
receiving a first value from a counter when the test signal is sent;
receiving a second value from the counter when the response signal is received;
determining a delay time for a first signal by subtracting the first value from the second value, wherein the first signal indicates a clock signal for a device coupled to a processor;
changing the delay time for the first signal based on a comparison of the first signal with a second signal, wherein the second signal indicates a system clock signal associated with the processor.
14. The system of claim 13 , wherein the comparison comprises comparing a propagation time of the first signal with a propagation time of the second signal.
15. The system of claim 13 , further comprising comparing a phase between the first signal and the second signal.
16. The system of claim 13 , wherein the processor includes the delay circuit.
17. The system of claim 13 , wherein the count is responsive to a supply voltage.
18. The system of claim 13 , wherein the count is responsive to temperature.
19. The system of claim 13 , wherein the comparison of the first signal with the second signal produces a voltage representative of the comparison.