Method for fabricating MOS-FET
View Patent ↗A method for fabricating MOS-FET using a SOI substrate includes a process of ion implantation of an impurity into a channel region in a SOI layer; and a process of channel-annealing in a non-oxidized atmosphere. In the ion implantation process, a concentration peak of the impurity is made to exist in the SOI layer. Moreover in the channel-annealing process, the impurity is distributed with a high concentration in the vicinity of the surface of the SOI layer under the following condition with the anneal temperature as T (K) and annealing time as t (minutes): 506×1000/ T −490< t <400×1000/ T −386.
1. A method for fabricating a MOS-FET using a SOI substrate, comprising:
a process of ion-implantation of an impurity into a channel region in a SOI layer, the SOI layer having a thickness, wherein a concentration peak of the implanted impurity in the SOI layer is at a vicinity of a midpoint of the thickness; and
a process of channel-annealing in a non-oxidized atmosphere, that moves the concentration peak of the implanted impurity to an upper surface of the SOI layer,
said channel-annealing is carried out at 600 to 750° C. for 5 to 90 minutes.
2. The method for fabricating a MOS-FET according to claim 1 , wherein a dose amount of said ion-implanted impurity is 1.0×10 12 cm −2 or more and 1.0×10 13 cm −2 or less.
3. The method for fabricating a MOS-FET according to claim 1 , wherein the SOI layer has a fully depleted type structure.
4. The method for fabricating a MOS-FET according to claim 1 , further comprising:
a process of introducing interstitial silicon into the channel region in the SOI layer by silicon implantation prior to said channel-annealing.
5. A method of fabricating a semiconductor device comprising:
ion-implanting an impurity into a channel region of an SOI layer, where the SOI layer has a thickness and has a first surface disposed on an insulating layer, a concentration peak of the implanted impurity in the SOI layer is at a vicinity of a midpoint of the thickness; and
heat treating the channel region in a non-oxidized atmosphere to move the concentration peak of the implanted impurity from the midpoint to a second surface of the SOI layer that is opposite the first surface,
said heat treatment is carried out at 600° C. to 750° C. for 5 to 90 minutes.
6. The method of claim 5 , wherein a dose amount of the implanted impurity is 1.0×10 12 cm −2 or more and 1.0×10 13 cm −2 or less.
7. The method of claim 5 , wherein the SOI layer is fully depleted.
8. The method of claim 5 , further comprising implanting interstitial silicon into the channel region prior to said heat treatment.