Post passivation interconnection schemes on top of IC chip
View Patent ↗A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
1. A chip comprising:
a silicon substrate;
a first internal circuit in or on said silicon substrate;
a driver, receiver or I/O circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first via over said silicon substrate and in said dielectric layer, wherein said first via is connected to a first terminal of said driver, receiver or I/O circuit;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;
a second via in said passivation layer and directly over said first via, wherein said second via is connected to said first via;
a third via in said passivation layer, wherein said third via is connected to said first interconnecting structure; and
a second interconnecting structure over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, and wherein said first terminal is connected to said first internal circuit through, in sequence, said first via, said second via, said second interconnecting structure, said third via and said first interconnecting structure.
2. The chip of claim 1 further comprising a second internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said first interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first via, said second via, said second interconnecting structure, said third via and said first interconnecting structure.
3. The chip of claim 1 further comprising a second internal circuit in or on said silicon substrate, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said second internal circuit, and a fourth via in said passivation layer, wherein said fourth via is connected to said second and third interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third via, said second interconnecting structure, said fourth via and said third interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first via, said second via, said second interconnecting structure, said fourth via and said third interconnecting structure.
4. The chip of claim 1 further comprising an ESD circuit in or on said silicon substrate, and a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit.
5. The chip of claim 4 , wherein said third interconnecting structure provides an access to an external clock for said ESD circuit and for said second terminal.
6. The chip of claim 4 , wherein said third interconnecting structure provides an access to an external signal for said ESD circuit and for said second terminal.
7. The chip of claim 1 , wherein said second interconnecting structure comprises an interconnect line having a thickness greater than 1 micrometer.
8. A chip comprising:
a silicon substrate;
a first internal circuit in or on said silicon substrate;
a driver, receiver or I/O circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first via over said silicon substrate and in said dielectric layer, wherein said first via is connected to a first terminal of said driver, receiver or I/O circuit;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;
a polymer layer over said passivation layer;
a second via in said polymer layer and directly over said first via, wherein said second via is connected to said first via;
a third via in said polymer layer, wherein said third via is connected to said first interconnecting structure; and
a second interconnecting structure over said passivation layer and in said polymer layer, wherein said second interconnecting structure is connected to said second and third vias, and wherein said first terminal is connected to said first internal circuit through, in sequence, said first via, said second via, said second interconnecting structure, said third via and said first interconnecting structure.
9. The chip of claim 8 further comprising a second internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said first interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first via, said second via, said second interconnecting structure, said third via and said first interconnecting structure.
10. The chip of claim 8 further comprising a second internal circuit in or on said silicon substrate, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said second internal circuit, and a fourth via in said polymer layer, wherein said fourth via is connected to said second and third interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third via, said second interconnecting structure, said fourth via and said third interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first via, said second via, said second interconnecting structure, said fourth via and said third interconnecting structure.
11. The chip of claim 8 further comprising an ESD circuit in or on said silicon substrate, and a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit.
12. The chip of claim 11 , wherein said third interconnecting structure provides an access to an external clock for said ESD circuit and for said second terminal.
13. The chip of claim 11 , wherein said third interconnecting structure provides an access to an external signal for said ESD circuit and for said second terminal.
14. The chip of claim 8 , wherein said polymer layer has a thickness greater than 2 micrometers.
15. A chip comprising:
a silicon substrate;
a first internal circuit in or on said silicon substrate;
a driver, receiver or I/O circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit;
a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;
a polymer layer over said passivation layer;
a first via in said polymer layer, wherein said first via is connected to said first interconnecting structure;
a second via in said polymer layer, wherein said second via is connected to said second interconnecting structure; and
a third interconnecting structure in said polymer layer, wherein said third interconnecting structure is connected to said first and second vias, and wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
16. The chip of claim 15 further comprising a second internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said second interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
17. The chip of claim 15 further comprising a second internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said second internal circuit, and a third via in said polymer layer, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.
18. The chip of claim 15 further comprising an ESD circuit in or on said silicon substrate, and a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit.
19. The chip of claim 18 , wherein said fourth interconnecting structure provides an access to an external clock for said ESD circuit and for said second terminal.
20. The chip of claim 18 , wherein said fourth interconnecting structure provides an access to an external signal for said ESD circuit and for said second terminal.