IP Library Granted Patent US 8,756,402
Granted Patent B2
US 8,756,402 · App. 11/855,383 · Granted Jun 17, 2014

Processing module, processor circuit, instruction set for processing data, and method for synchronizing the processing of codes

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Quick Facts
Patent No.
US 8,756,402
App. No.
11/855,383
Granted
Jun 17, 2014
Kind
B2
Abstract

A processing module, a processor circuit, an instruction set for processing data, and a method for synchronizing the processing of codes are provided. In an embodiment of the invention, a processing module for processing instructions, the instructions relating to user data and control data according to a communication protocol. The processing module includes a first processing circuit configured to process the instructions relating to the control data, and a second processing circuit configured to process the instructions relating to the user data.

Claims (23)

1. A processing module for processing user data instructions and control data instructions according to a communication protocol, the processing module comprising a first processor and a second processor wherein:

the first processor is configured to generate user data instructions including a synchronization instruction and control data instructions according to a first process to generate independently from the first process at least further user data instructions including a synchronization instruction and control data instructions according to a second process, to provide the user data instructions and the further user data instructions to be processed by the second processor to the second processor, and to signal validity and completeness of the generated further user data instructions by setting a semaphore; and

the second processor is configured to execute the synchronization instruction to check the semaphore after finishing processing of user data instructions, to process the further user data instructions if the semaphore is set, and to enter an idle state if the semaphore is not set.

2. The processing module of claim 1 ,

wherein the first processor comprises a microcontroller, and

wherein the second processor comprises a co-processor.

3. The processing module of claim 1 , wherein the communication protocol is a communication protocol of a mobile radio communication standard.

4. The processing module of claim 1 , wherein the communication protocol comprises a radio link control layer and a medium access control layer, and the instructions handle data of the radio link control layer and the medium access control layer.

5. The processing module of claim 1 , wherein the processing module further comprises a memory configured to store the instructions provided to the second processor.

6. The processing module of claim 1 , wherein the processing module further comprises:

an interface to a processing module external memory configured to store user data of a communication layer in a form of a source bit stream; and

an interface to a memory in which output data is stored in a form of a target bit stream generated by the second processor according to the instructions.

7. A method for synchronizing the processing of codes, the method comprising:

at least two processes each generating independently from each other codes comprising user data instructions and a synchronization instruction for processing user data according to a communication protocol;

a second of the two processes signaling validity and completeness of generated further code comprising user data instructions by setting a semaphore;

a further process executing the synchronization instruction to check the semaphore after processing of code comprising user data instructions, and

processing further code comprising user data instructions of the second of the at least two processes if the semaphore is set, and entering an idle state if the semaphore is not set.

8. The method of claim 7 , further comprising:

a first of the at least two processes signaling release of its code for processing; and

immediately processing the released code.

9. The method of claim 7 , wherein the code is processed by a co-processor.

10. The method of claim 7 , wherein the code is user data code of a communication protocol layer.

11. The method of claim 10 , wherein the communication protocol layer is a radio link control and/or media access control layer of a mobile radio communication standard.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2012
From: INFINEON TECHNOLOGIES DELTA GMBH
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027531/0108 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE TO 09/30/2009 PREVIOUSLY RECORDED ON REEL 026685 FRAME 0165. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2011
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES DELTA GMBH
Reel/Frame 026908/0766 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2011
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES DELTA GMBH
Reel/Frame 026685/0165 →
CORRECTIVE ASSIGNMENT TO CORRECT THE STATE/COUNTRY PREVIOUSLY RECORDED ON REEL 020146 FRAME 0271. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 14, 2008
From: STEINERT, MARIO; HEIN, WERNER; ITJESHORST, RALF
To: INFINEON TECHNOLOGIES AG
Reel/Frame 020358/0993 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2007
From: STEINERT, MARIO; HEIN, WERNER; ITJESHORST, RALF
To: INFINEON TECHNOLOGIES AG
Reel/Frame 020146/0271 →