Heterogeneous configurable integrated circuit
View Patent ↗A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
1. A system comprising:
a plurality of programmable logic blocks;
a plurality of special-purpose blocks;
a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, wherein the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system;
a memory controller operatively connected to the plurality of special-purpose blocks and the plurality of programmable logic blocks using the high-speed mesh interconnect fabric, wherein the memory controller is configured to transfer data between an external memory and at least one selected from a group consisting of the plurality of special-purpose blocks and the plurality of programmable logic blocks; and
a general purpose input/output block operatively configured to transfer data between the external memory and at least one selected from a group consisting of the memory controller, the plurality of special-purpose blocks, and the plurality of programmable logic blocks,
wherein the general purpose input/output block comprises:
a converter for executing a double data rate to single data rate conversion of the transferred data;
a transmit delay lock loop for de-skewing source-synchronous signals associated with the transferred data;
a receive delay lock loop for de-skewing source-synchronous signals associated with the transferred data; and
error correcting code logic for error detection and error correction of the transferred data.
2. The system of claim 1 , wherein the configurable high-speed mesh interconnect fabric operates at a first clock frequency and a special-purpose block of the plurality of special-purpose blocks operates at a second clock frequency.
3. The system of claim 1 , wherein the configurable high-speed mesh interconnect fabric operates at a first clock frequency and a programmable logic block of the plurality of the programmable logic blocks operates at a second clock frequency.
4. The system of claim 1 , wherein a special-purpose block of the plurality of special-purpose blocks is a frame parser comprising a plurality of frame parser units forming a parser ring, wherein each of the plurality of frame parser units is controlled using a dedicated instruction memory.
5. The system of claim 1 , wherein a special-purpose block of the plurality of special-purpose blocks is a reconfigurable content addressable memory comprising a classification engine configured to classify a frame based on at least one selected from a group consisting of a header and a payload of the frame.
6. The system of claim 1 , farther comprising:
a single port ram unit; and
a double port ram unit,
wherein at least one selected from a group consisting of the single port ram unit and the double port ram unit is accessible to the plurality of special-purpose blocks and the plurality of programmable logic blocks using the high-speed mesh interconnect fabric.
7. The system of claim 1 , farther comprising:
a packet buffer; and
a priority queue manager operatively connected to the high-speed mesh interconnect fabric and configured to manage a packet stored in the packet buffer to satisfy a quality of service guarantee.
8. The system of claim 1 , further comprising:
a reconfigurable traffic scheduler operatively connected to the high-speed mesh interconnect fabric and accessible by at least one selected from the group consisting of the plurality of special-purpose blocks and the plurality of programmable logic blocks for satisfying a plurality of quality of service treatments.
9. The system of claim 1 , wherein a special-purpose block of the plurality of special-purpose blocks is a packet editor configured to modify a packet by performing at least one selected from a group consisting of a bit transformation and a byte transformation on the packet.
10. The system of claim 1 , wherein a special-purpose block of the plurality of special purpose blocks is a reconfigurable arithmetic logic unit configured to perform at least one selected from a group consisting of cyclic redundancy check, hashing, and checksum.
11. The system of claim 1 , wherein a special purpose block of the plurality of special purpose blocks is a digital signal processing unit configured to perform at least one selected from a group consisting of voice compression, video compression, telephony signaling, and echo cancellation on an incoming packet.