IP Library Granted Patent US 8,127,203
Granted Patent B2
US 8,127,203 · App. 11/856,069 · Granted Feb 28, 2012

Method, data processing apparatus and wireless device

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Quick Facts
Patent No.
US 8,127,203
App. No.
11/856,069
Granted
Feb 28, 2012
Kind
B2
Abstract

Embodiments of the invention relate generally to a method, to a data processing apparatus and to a wireless device. In an embodiment of the invention a data processing apparatus is provided. The data processing apparatus may include a chip-integrated unit to select a check location of an external memory and to generate a check value, an internal memory associated with the chip-integrated unit, the internal memory to save the check location and the check value, and an external memory coupled to the chip-integrated unit, the external memory to store the check value at the check location.

Claims (31)

1. A method, comprising:

selecting a check location of an external memory;

generating a check value;

saving the check location and the check value in an internal memory; and

storing the check value at the check location in the external memory.

2. The method as recited in claim 1 , wherein the selecting includes generating an address which is within an address space of the external memory.

3. The method as recited in claim 1 , wherein the selecting includes randomly selecting the check location of the external memory.

4. The method as recited in claim 1 , wherein the generating includes randomly generating the check value.

5. The method as recited in claim 1 , wherein the saving includes saving an address specifying the check location.

6. The method as recited in claim 1 , further comprising reading an original content from the check location prior to the storing the check value at the check location in the external memory.

7. The method as recited in claim 6 , further comprising saving the original content in an internal memory.

8. The method as recited in claim 6 , further comprising restoring the original content at the check location.

9. The method as recited in claim 1 , further comprising reading a check content from the check location after the storing the check value at the check location in the external memory.

10. The method as recited in claim 9 , further comprising comparing the check content to the check value.

11. The method as recited in claim 9 , further comprising initializing a wake-up from a sleep mode.

12. The method as recited in claim 11 , wherein the initializing the wake-up from the sleep mode is performed after the saving the check location and the check value in the internal memory and after the storing the check value at the check location in the external memory and further wherein the reading the check content is performed after the initializing.

13. The method as recited in claim 11 , further comprising verifying whether the check value stored at the check location in the external memory has been changed during the sleep mode.

14. The method as recited in claim 1 , wherein the method is performed using a plurality of check locations and a plurality of check values.

15. A data processing apparatus, comprising:

a chip-integrated unit to select a check location of an external memory and to generate a check value;

an internal memory associated with the chip-integrated unit, the internal memory to save the check location and the cheek value; and

an external memory coupled to the chip-integrated unit, the external memory to store the check value at the check location.

16. The data processing apparatus as recited in claim 15 , wherein the chip-integrated unit includes a microprocessor.

17. The data processing apparatus as recited in claim 15 , wherein the chip-integrated unit includes a dedicated hardware unit to select the check location of the external memory.

18. The data processing apparatus as recited in claim 15 , wherein the chip-integrated unit includes a dedicated hardware unit to generate the check value.

19. The data processing apparatus as recited in claim 15 , wherein the chip-integrated unit includes a dedicated hardware unit to save at least one of the check location and the check value.

20. The data processing apparatus as recited in claim 15 , wherein the chip-integrated unit includes an address generator to generate an address which is within an address space of the external memory.

21. The data processing apparatus as recited in claim 15 , wherein the chip-integrated unit includes a random number generator.

22. The data processing apparatus as recited in claim 15 , the internal memory further to save an address specifying the check location.

23. The data processing apparatus as recited in claim 15 , further comprising a chip-integrated compare unit to compare a check content read from the check location to the check value.

24. A wireless device comprising a data processing apparatus as recited in claim 15 .

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: INFINEON TECHNOLOGIES AG
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027548/0623 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2008
From: HILDEBRAND, UWE
To: INFINEON TECHNOLOGIES AG
Reel/Frame 020324/0380 →