Post passivation interconnection schemes on top of IC chip
View Patent ↗A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
1. A chip comprising:
a silicon substrate;
a first internal circuit in or on said silicon substrate;
a second internal circuit in or on said silicon substrate;
a third internal circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first local power distribution network over said silicon substrate and in said dielectric layer, wherein said first local power distribution network is connected to said first internal circuit and to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said first local power distribution network;
a second local power distribution network over said silicon substrate and in said dielectric layer, wherein said second local power distribution network is connected to said third internal circuit;
a passivation layer over said dielectric layer;
a first via in said passivation layer, wherein said first via is connected to said first local power distribution network;
a second via in said passivation layer, wherein said second via is connected to said second local power distribution network; and
a global power distribution network over said passivation layer, wherein said global power distribution network is connected to said first and second vias, wherein said first internal circuit is connected to said third internal circuit through, in sequence, said first local power distribution network, said first via, said global power distribution network, said second via and said second local power distribution network, and wherein said second internal circuit is connected to said third internal circuit through, in sequence, said first local power distribution network, said first via, said global power distribution network, said second via and said second local power distribution network.
2. The chip of claim 1 further comprising a fourth internal circuit in or on said silicon substrate, wherein said first local power distribution network is connected to said fourth internal circuit, wherein said first internal circuit is are connected to said fourth internal circuit through said first local power distribution network, wherein said second internal circuit is connected to said fourth internal circuit through said first local power distribution network, wherein said fourth internal circuit is connected to said third internal circuit through, in sequence, said first local power distribution network, said first via, said global power distribution network, said second via and said second local power distribution network.
3. The chip of claim 1 further comprising a fourth internal circuit in or on said silicon substrate, a third local power distribution network over said silicon substrate and in said dielectric layer, wherein said third local power distribution network is connected to said fourth internal circuit, and a third via in said passivation layer, wherein said third via is connected to said third local power distribution network and to said global power distribution network, wherein said first internal circuit is connected to said fourth internal circuit through, in sequence, said first local power distribution network, said first via, said global power distribution network, said third via and said third local power distribution network, wherein said second internal circuit is connected to said fourth internal circuit through, in sequence, said first local power distribution network, said first via, said global power distribution network, said third via and said third local power distribution network, wherein said third internal circuit is connected to said fourth internal circuit through, in sequence, said second local power distribution network, said second via, said global power distribution network, said third via and said third local power distribution network.
4. The chip of claim 1 further comprising an ESD circuit in or on said silicon substrate, wherein said ESD circuit is connected to said first, second and third internal circuits through said global power distribution network.
5. The chip of claim 1 further comprising a polymer comprising a portion over said global power distribution network.
6. The chip of claim 1 further comprising a polymer having a thickness greater than 2 micrometers.
7. The chip of claim 1 , wherein said global power distribution network comprises an interconnecting line having a thickness greater than 1 micrometer.
8. The chip of claim 1 , wherein said passivation layer comprises a nitride layer.
9. The chip of claim 1 , wherein said passivation layer comprises a nitride layer and an oxide layer.
10. A chip comprising:
a silicon substrate;
a first internal circuit in or on said silicon substrate;
a second internal circuit in or on said silicon substrate;
a third internal circuit in or on said silicon substrate;
a fourth internal circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first local power distribution network over said silicon substrate and in said dielectric layer, wherein said first local power distribution network is connected to said first internal circuit and to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said first local power distribution network;
a second local power distribution network over said silicon substrate and in said dielectric layer, wherein said second local power distribution network is connected to said third internal circuit and to said fourth internal circuit, wherein said third internal circuit is connected to said fourth internal circuit through said second local power distribution network;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer;
a first via in said passivation layer, wherein said first via is connected to said first local power distribution network;
a second via in said passivation layer, wherein said second via is connected to said second local power distribution network; and
a global power distribution network over said passivation layer, wherein said global power distribution network is connected to said first and second vias, wherein said first internal circuit is connected to said third and fourth internal circuits through, in sequence, said first local power distribution network, said first via, said global power distribution network, said second via and said second local power distribution network, and wherein said second internal circuit is connected to said third and fourth internal circuits through, in sequence, said first local power distribution network, said first via, said global power distribution network, said second via and said second local power distribution network.
11. The chip of claim 10 further comprising a fifth internal circuit in or on said silicon substrate, wherein said first local power distribution network is connected to said fifth internal circuit, wherein said first internal circuit is connected to said fifth internal circuit through said first local power distribution network, wherein said second internal circuit is connected to said fifth internal circuit through said first local power distribution network, wherein said fifth internal circuit is connected to said third and fourth internal circuits through, in sequence, said first local power distribution network, said first via, said global power distribution network, said second via and said second local power distribution network.
12. The chip of claim 10 further comprising a fifth internal circuit in or on said silicon substrate, a third local power distribution network over said silicon substrate and in said dielectric layer, wherein said third local power distribution network is connected to said fifth internal circuit, and a third via in said passivation layer, wherein said third via is connected to said third local power distribution network and to said global power distribution network, wherein said first internal circuit is connected to said fifth internal circuit through, in sequence, said first local power distribution network, said first via, said global power distribution network, said third via and said third local power distribution network, wherein said second internal circuit is connected to said fifth internal circuit through, in sequence, said first local power distribution network, said first via, said global power distribution network, said third via and said third local power distribution network, wherein said third internal circuit is connected to said fifth internal circuit through, in sequence, said second local power distribution network, said second via, said global power distribution network, said third via and said third local power distribution network, and wherein said fourth internal circuit is connected to said fifth internal circuit through, in sequence, said second local power distribution network, said second via, said global power distribution network, said third via and said third local power distribution network.
13. The chip of claim 10 further comprising an ESD circuit in or on said silicon substrate, wherein said ESD circuit is connected to said first, second, third and fourth internal circuits through said global power distribution network.
14. The chip of claim 10 further comprising a polymer comprising a portion over said global power distribution network.
15. The chip of claim 14 , wherein said polymer has a thickness greater than 2 micrometers.
16. The chip of claim 10 , wherein said global power distribution network comprises an interconnecting line having a thickness greater than 1 micrometer.
17. A chip comprising:
a silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer;
a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure comprises an electroplated damascene metal;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer;
a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;
a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure;
a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first interconnecting structure is connected to said second interconnecting structure through, in sequence, said first via, said third interconnecting structure and said second via, wherein a top surface of said third interconnecting structure has no access for external connection, wherein said third interconnecting structure comprises an electroplated metal; and
a polymer layer over said passivation layer, wherein said polymer layer has a portion over said third interconnecting structure.
18. The chip of claim 17 further comprising a first internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said first internal circuit, and a second internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
19. The chip of claim 17 , wherein said third interconnecting structure comprises an interconnect line having a thickness greater than 1 micrometer.
20. The chip of claim 17 , wherein said third interconnecting structure comprises a signal interconnect connecting said first interconnecting structure to said second interconnecting structure.
21. The chip of claim 17 , wherein said third interconnecting structure comprises a clock interconnect connecting said first interconnecting structure to said second interconnecting structure.
22. The chip of claim 17 , wherein said third interconnecting structure is an integral continuous piece of metal over said passivation layer.