Post passivation interconnection schemes on top of IC chip
View Patent ↗A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
1. A chip comprising:
a silicon substrate;
a first internal circuit in or on said silicon substrate;
an ESD circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit;
a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;
a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;
a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; and
a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a ground bus over said passivation layer, wherein said ground bus is connected to said first and second vias, wherein said ESD circuit is connected to said first internal circuit through said ground bus.
2. The chip of claim 1 further comprising a second internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said second interconnecting structure, wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
3. The chip of claim 2 further comprising a third internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said third internal circuit, and a third via in said passivation layer, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first internal circuit is connected to said third internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, wherein said second internal circuit is connected to said third internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, wherein said ESD circuit is connected to said third internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.
4. The chip of claim 1 further comprising a second internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said second internal circuit, and a third via in said passivation layer, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.
5. The chip of claim 1 further comprising a polymer layer over said passivation layer, wherein said polymer layer comprises a portion over said third interconnecting structure.
6. A chip comprising:
a silicon substrate;
a first internal circuit in or on said silicon substrate;
an ESD circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit;
a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride, wherein one of multiple openings in said passivation layer has a width between 0.5 and 30 micrometers;
a first via in one of said multiple openings, wherein said first via is connected to said first interconnecting structure;
a second via in one of said multiple openings, wherein said second via is connected to said second interconnecting structure; and
a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a ground bus over said passivation layer, wherein said ground bus is connected to said first and second vias, wherein said ESD circuit is connected to said first internal circuit through said ground bus.
7. The chip of claim 6 further comprising a second internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said second interconnecting structure, wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
8. The chip of claim 7 further comprising a third internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said third internal circuit, and a third via in one of said multiple openings, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first internal circuit is connected to said third internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, wherein said second internal circuit is connected to said third internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, wherein said ESD circuit is connected to said third internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.
9. The chip of claim 6 further comprising a second internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said second internal circuit, and a third via in one of said multiple openings, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.
10. The chip of claim 6 further comprising a polymer layer over said passivation layer, wherein said polymer layer comprises a portion over said third interconnecting structure.
11. A chip comprising:
a silicon substrate;
a first internal circuit in or on said silicon substrate;
an ESD circuit in or on said silicon substrate;
a dielectric system over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric system, wherein said first interconnecting structure is connected to said ESD circuit;
a second interconnecting structure over said silicon substrate and in said dielectric system, wherein said second interconnecting structure is connected to said first internal circuit;
multiple metal layers in said dielectric system, wherein said dielectric system comprises multiple dielectric layers between said multiple metal layers;
a passivation layer over said dielectric system and over said multiple metal layers, wherein said passivation layer comprises a nitride;
a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;
a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; and
a third interconnecting structure over said passivation layer, wherein said third interconnecting structure comprises an interconnect line having a thickness greater than 1 micrometer, wherein said third interconnecting structure is connected to said first and second vias, wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a ground bus over said passivation layer, wherein said ground bus is connected to said first and second vias, wherein said ESD circuit is connected to said first internal circuit through said ground bus.
12. The chip of claim 11 further comprising a second internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said second interconnecting structure, wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
13. The chip of claim 11 further comprising a second internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric system, wherein said fourth interconnecting structure is connected to said second internal circuit, and a third via in said passivation layer, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.
14. The chip of claim 11 further comprising a polymer layer over said passivation layer, wherein said polymer layer comprises a portion over said third interconnecting structure.