Post passivation interconnection schemes on top of IC chip
View Patent ↗A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
1. A method for fabricating a chip, comprising:
providing a silicon substrate, a first internal circuit in or on said silicon substrate, a second internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit, and a passivation layer over said dielectric layer; and
forming a clock bus over said passivation layer, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said clock bus and said second interconnecting structure, and wherein said forming said clock bus comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.
2. The method of claim 1 , wherein said forming said first metal layer comprises a sputtering process.
3. The method of claim 1 , wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process.
4. The method of claim 1 , wherein said first and second interconnecting structures are formed by a process comprising a sputtering process and an etching process.
5. The method of claim 1 further comprising forming a polymer layer over said passivation layer, wherein said clock bus is in said polymer layer.
6. The method of claim 5 , wherein said polymer layer has a thickness greater than 2 micrometers.
7. The method of claim 1 , wherein said clock bus has a thickness greater than 1 micrometer.
8. The method of claim 1 , wherein said passivation layer comprises a topmost insulating nitride layer of said chip.
9. The method of claim 1 , wherein said passivation layer comprises a nitride layer and an oxide layer.
10. The method of claim 1 , wherein said passivation layer comprises a nitride layer.
11. The method of claim 1 further comprising providing a driver, receiver or I/O circuit in or on said silicon substrate, wherein said driver, receiver or I/O circuit has a first terminal connected to said first and second internal circuits through said clock bus.
12. The method of claim 11 further comprising providing an electrostatic discharge (ESD) circuit in or on said silicon substrate, wherein said electrostatic discharge circuit is connected to a second terminal of said driver, receiver or I/O circuit.
13. The method of claim 12 further comprising providing an external connection point connected to said ESD circuit and to said second terminal.