System and method for aligning data in a network environment
View Patent ↗In a network environment, a first master timing generator generates a first frame reference signal and a second master timing generator generates a second frame reference signal. A first data source generates a first data source signal, a first frame source signal, and a first clock source signal in response to a selected one of the first and second frame reference signals. Similarly, a second data source generates a second data source signal, a second frame source signal, and a second clock source signal in response to a selected one of the first and second frame reference signals. A timing recovery circuit generates a recovered reference signal and a recovered clock signal in response to a selected one of the first and second frame reference signals. A phase aligner stores the first data source signal in response to the first frame source signal and the first clock source signal. The phase aligner also stores the second data source signal in response to the second frame source signal and the second clock source signal. The phase aligner aligns a phase of the first data source signal with a phase of the second data source signal in response to the recovered reference signal and the recovered clock signal.
1. A system for aligning data, comprising:
means for storing a first data source signal in a first buffer element, the first data source signal being associated with one of a first frame reference signal and a second frame reference signal;
means for storing a second data source signal in a second buffer element, the second data source signal being associated with one of the first frame reference signal and the second frame reference signal;
means for outputting the first and second data source signals in alignment with each other in response to a recovered reference signal and a recovered clock signal, the recovered reference signal and the recovered clock signal being associated with one of the first and second frame reference signals.
2. The system of claim 1 , further comprising:
means for generating a first write address for the first buffer element to store the first data source signal in response to a first frame source signal and a first clock source signal, the first frame source signal and the first clock source signal being associated with the first data source signal;
means for generating a second write address for the second buffer element to store the second data source signal in response to a second frame source signal and a second clock source signal, the second frame source signal and the second clock source signal being associated with the second data source signal.
3. The system of claim 1 , further comprising:
means for placing a known byte of the first and second data source signals into a known location of the respective first and second buffer elements.
4. The system of claim 1 , further comprising:
means for generating a read address to output the first and second data source signals from the respective first and second buffer elements in response to the recovered reference signal and the recovered clock signal.
5. The system of claim 1 , further comprising:
means for identifying a framing pattern in each of the first and second data source signals stored in the first and second buffers.
6. The system of claim 1 , further comprising:
means for generating a slip signal to control a read counter associated with each of the first and second buffer elements such that an output from each of the first and second buffers aligns to the recovered reference signal and the recovered clock signal.
7. The system of claim 1 , further comprising:
means for filtering out bit errors in the first and second data source signals.
8. A method for aligning data, comprising:
storing a first data source signal in a first buffer element, the first data source signal being associated with one of a first frame reference signal and a second frame reference signal;
storing a second data source signal in a second buffer element, the second data source signal being associated with one of the first frame reference signal and the second frame reference signal;
outputting the first and second data source signals in alignment with each other in response to a recovered reference signal and a recovered clock signal, the recovered reference signal and the recovered clock signal being associated with one of the first and second frame reference signals.
9. The method of claim 8 , further comprising:
generating a first write address for the first buffer element to store the first data source signal in response to a first frame source signal and a first clock source signal, the first frame source signal and the first clock source signal being associated with the first data source signal;
generating a second write address for the second buffer element to store the second data source signal in response to a second frame source signal and a second clock source signal, the second frame source signal and the second clock source signal being associated with the second data source signal.
10. The method of claim 8 , further comprising:
placing a known byte of the first and second data source signals into a known location of the respective first and second buffer elements.
11. The method of claim 8 , further comprising:
generating a read address to output the first and second data source signals from the respective first and second buffer elements in response to the recovered reference signal and the recovered clock signal.
12. The method of claim 8 , further comprising:
identifying a framing pattern in each of the first and second data source signals stored in the first and second buffers.
13. The method of claim 8 , further comprising:
generating a slip signal to control a read counter associated with each of the first and second buffer elements such that an output from each of the first and second buffers aligns to the recovered reference signal and the recovered clock signal.
14. The method of claim 8 , further comprising:
filtering out bit errors in the first and second data source signals.
15. A computer readable medium including code for aligning data, the code operable to:
store a first data source signal in a first buffer element, the first data source signal being associated with one of a first frame reference signal and a second frame reference signal;
store a second data source signal in a second buffer element, the second data source signal being associated with one of the first frame reference signal and the second frame reference signal;
output the first and second data source signals in alignment with each other in response to a recovered reference signal and a recovered clock signal, the recovered reference signal and the recovered clock signal being associated with one of the first and second frame reference signals.
16. The computer readable medium of claim 15 , wherein the code is further operable to:
generate a first write address for the first buffer element to store the first data source signal in response to a first frame source signal and a first clock source signal, the first frame source signal and the first clock source signal being associated with the first data source signal;
generate a second write address for the second buffer element to store the second data source signal in response to a second frame source signal and a second clock source signal, the second frame source signal and the second clock source signal being associated with the second data source signal.
17. The computer readable medium of claim 15 , wherein the code is further operable to:
place a known byte of the first and second data source signals into a known location of the respective first and second buffer elements.
18. The computer readable medium of claim 15 , wherein the code is further operable to:
generate a read address to output the first and second data source signals from the respective first and second buffer elements in response to the recovered reference signal and the recovered clock signal.
19. The computer readable medium of claim 15 , wherein the code is further operable to:
identify a framing pattern in each of the first and second data source signals stored in the first and second buffers.
20. The computer readable medium of claim 15 , wherein the code is further operable to:
generate a slip signal to control a read counter associated with each of the first and second buffer elements such that an output from each of the first and second buffers aligns to the recovered reference signal and the recovered clock signal.