Variable gain amplifier having dual gain control

1. An electronic amplifier circuit comprising:

a differential amplifier having a pair of transistors accepting a differential input signal at base nodes of the transistor pair;

a degeneration resistance coupled between emitters of the pair of transistors, the degeneration resistance comprising a first field effect transistor (FET);

a load resistance coupled between collectors of the pair of transistors, the load resistance comprising a second FET; and,

a control circuit for increasing the gain factor of the differential amplifier by decreasing the degeneration resistance and increasing the load resistance

wherein the control circuit receives a desired gain control signal and responsively generates a first gate-voltage control signal for controlling the degeneration resistance and generates a second gate-voltage control signal for controlling the load resistance; and

wherein the control circuit converts the desired gain control signal to a first and second current signal, and converts the first and second current signal to the first gate-control voltage and the second gate-control voltage, respectively.

2. The electronic amplifier circuit of claim 1 wherein the degeneration resistance comprises a fixed resistor in parallel with the first FET.

3. The electronic amplifier circuit of claim 1 wherein the first FET is an N-type FET and the load resistance is a P-type FET.

4. The electronic amplifier circuit of claim 1 wherein the control circuit converts the first and second current signals to the first gate-control voltage and the second gate-control voltage by passing the first and second current signals through first and second matching FET, respectively.

5. The electronic amplifier circuit of claim 1 wherein the control circuit includes a differential current steering circuit to convert a gain control voltage to a pair of gain control current signals, and a matching FET circuit for converting the pair of gain control current signals into a first gate-voltage control signal for controlling the degeneration resistance and a second gate-voltage control signal for controlling the load resistance.

6. The electronic amplifier circuit of claim 5 wherein the pair of gain control current signals vary in direct proportion to the gain control voltage, and wherein the first gate-control voltage and the second gate-control voltage vary in response to the pair of gain control current signals and in response to V TH associated with the matching FET circuit.

7. A method of controlling the gain of a differential pair transistor amplifier comprising:

coupling emitters of the differential-pair transistors with a degeneration resistance including a degeneration FET;

coupling collectors of the differential-pair transistors with a load resistance including a load FET; and

increasing a gain factor of the differential-pair transistors by simultaneously decreasing the degeneration resistance and increasing the load resistance;

wherein the gain is increased in response to a desired gain control signal by converting the desired gain control signal into a first gate-voltage control signal for controlling the degeneration resistance and a second gate-voltage control signal for controlling the load resistance; and

wherein the desired gain control signal is first converted to a first and second current signal, and the first and second current signals are converted to the first gate-control voltage and the second gate-control voltage, respectively.

8. The method of claim 7 , wherein the load FET is a P-type FET and the degeneration FET is an N-type FET.

9. The method of claim 7 wherein the first and second current signals are converted to the first gate-control voltage and the second gate-control voltage, respectively, by passing the first and second current signals through as first and second matching FET to establish the first gate-control voltage and the second gate-control voltage on gate nodes of the first and second matching FETs, respectively.

10. The method of claim 7 wherein the degeneration resistance includes a resistive element in parallel with the degeneration FET, and the degeneration resistance is decreased by increasing a gate voltage on the degeneration FET.

11. The method of claim 7 wherein simultaneously decreasing the degeneration resistance and increasing the load resistance comprises:

generating a differential current signal in response to a gain control signal;

passing the differential current signal through a pair of matching FETs; and,

applying a first and second gate-voltage signal obtained from the pair of matching FETs t to the degeneration FET and the load FET, respectively.

12. The method of claim 11 wherein each of the matching FETs have threshold voltages V TH substantially equal to the threshold voltages of the degeneration FET and the load FET.

13. The method of claim 7 wherein the load FET provides an amplifier transfer function pole at a location approximately equal to an amplifier transfer function zero associated with the degeneration FET.

14. A method of controlling the gain of a differential pair transistor amplifier comprising:

coupling emitters of the differential-pair transistors with a degeneration FET; and,

adjusting a gain factor of the differential-pair transistors by changing a resistance of the degeneration FET by (i) generating a current signal in response to a gain control signal, (ii) passing the current signal through a matching FET, and (iii) applying a gate-voltage signal obtained from the matching FET to a gate node of the degeneration FET.

15. The method of claim 14 wherein the matching FET has a threshold voltage V TH substantially equal to the threshold voltage of the degeneration FET.

16. The method of claim 14 wherein a drain node of the matching FET is voltage matched to a node of the degeneration FET, and the gate-voltage signal is induced on the gate node of the matching FET in response to the current signal passing through the matching FET.