III-nitride power semiconductor device having a programmable gate
View Patent ↗A III-nitride semiconductor device which includes a charged floating gate electrode.
1. A power semiconductor device including a programmed threshold voltage, said semiconductor device comprising:
a first III-nitride semiconductor body having a band gap;
a second III-nitride semiconductor body having another band gap over said first III-nitride semiconductor body to form a two dimensional electron gas;
first and second power electrodes coupled to said second III-nitride semiconductor body;
a gate arrangement disposed over said second III-nitride semiconductor body, the gate arrangement including a non-volatile charged floating gate electrode, and a gate electrode arranged over said non-volatile charged floating gate electrode, said non-volatile charged floating gate electrode maintaining said programmed threshold voltage when a high current is present in said two dimensional electron gas of said power semiconductor device.
2. The semiconductor device of claim 1 , wherein said first III-nitride semiconductor body is comprised of one semiconductor alloy from the InAlGaN system, and said second III-nitride semiconductor body is comprised of another semiconductor alloy from the InAlGaN system.
3. The semiconductor device of claim 1 , wherein said first III-nitride semiconductor body is comprised of GaN, and said second III-nitride semiconductor body is comprised of AlGaN.
4. The semiconductor device of claim 1 , further comprising a gate insulation body disposed between said charged floating gate electrode and said second III-nitride semiconductor body.
5. The semiconductor device of claim 4 , wherein said one insulation body is comprised of silicon nitride.
6. The semiconductor device of claim 1 , wherein said charged floating gate electrode is charged to interrupt said two dimensional electron gas.
7. The semiconductor device of claim 1 , wherein the threshold voltage of said two dimensional electron gas beneath said gate arrangement is set by the charge in said charged floating gate electrode.
8. The semiconductor device of claim 1 , further comprising a silicon substrate.
9. The semiconductor device of claim 1 , further comprising a silicon carbide substrate.
10. The semiconductor device of claim 9 , further comprising a sapphire substrate.
11. The semiconductor device of claim 1 , wherein said semiconductor device is a discrete power device.
12. The semiconductor device of claim 1 , wherein said semiconductor device is an integrated circuit.
13. The semiconductor device of claim 1 , wherein said charged floating gate electrode is negatively charged.
14. The semiconductor device of claim 1 , further comprising another gate arrangement said another gate arrangement including a charged floating gate electrode that is charged differently than said charged floating gate electrode of said gate arrangement and a gate electrode that is shorted to said gate electrode of said gate arrangement.
15. The semiconductor device of claim 1 , wherein said charged floating gate electrode is rechargeable.
16. A method of fabricating a semiconductor device including a programmed threshold voltage, comprising:
disposing one III-nitride semiconductor body having one band gap over another III-nitride semiconductor body of another band gap to obtain a two dimensional electron gas;
forming a gate insulation body over said second III-nitride semiconductor body;
forming a floating gate electrode over said gate insulation body;
disposing a gate electrode over said floating gate electrode; and
charging said floating gate electrode to obtain a non-volatile charged floating gate electrode;
maintaining said programmed threshold voltage when a high current is present in said two dimensional electron gas of said semiconductor device.
17. The method of claim 16 , wherein said floating gate electrode is charged to interrupt said two dimensional electron gas.
18. The method of claim 16 , wherein said floating gate electrode is charged to vary the threshold voltage beneath said gate arrangement.
19. The method of claim 16 , wherein said floating gate is charged using a tunneling method.
20. The method of claim 17 , wherein said floating gate electrode is charged using hot electron injection.