Comparing counter contents for timing critical applications

1. A method, comprising:

providing an electrical circuit comprising a first counter circuit A, a second counter circuit B, a flip-flop circuit, a first OR gate, a second OR gate, and a logic circuit, wherein an output of said first counter circuit A is electrically connected to a first input of said logic circuit, wherein an output of said second counter circuit B is electrically connected to a second input of said logic circuit, wherein an output of said logic circuit is electrically connected to an enable input E on said flip-flop circuit, wherein said first OR gate is electrically connected to an input PRE of the flip-flop circuit, and wherein said second OR gate is electrically connected to an input RST of the flip-flop circuit;

receiving by said first counter circuit A, a first enable signal INC_A;

generating by said first counter circuit A, a first output signal SIG_A;

receiving by said second counter circuit B, a second enable signal INC_B;

generating by said second counter circuit B, a second output signal SIG_B;

comparing by said first enable signal INC_A and said second enable signal INC_B said first output signal SIG_A to said second output signal SIG_B;

generating by said flip-flop circuit, a first status signal defining a first relationship between said first output signal SIG_A and said second output signal SIG_B;

generating by said logic circuit, a second status signal defining a second relationship between said first output signal SIG_A and said second output signal SIG_B;

receiving by said first OR gate, a signal PRE_A and a signal RST_B;

generating, by said first OR gate from said signal PRE_A and said signal RST_B, a first ORed signal;

applying by said first OR gate, said first ORed signal to said input PRE of the flip-flop circuit;

receiving by said second OR gate, a signal PRE_B and a signal RST_A;

generating by said second OR gate from said signal PRE_B and said signal RST_A a second ORed signal; and

applying by said second OR gate, said second ORed signal to said input RST of the flip-flop circuit.

2. The method of claim 1 , further comprising:

generating on said output of said logic circuit said second status comprising a signal SIG_A=B representing said first output signal SIG_A being equal to said second output signal SIG_B; and

applying said signal SIG_A=B to said enable input on said flip-flop circuit.

3. The method of claim 2 , wherein said signal SIG_A=B comprises a logical high.

4. The method of claim 2 , further comprising:

providing a first logic gate, wherein an output of said first logic gate is electrically connected to a data input D of said flip-flop circuit; and

receiving by said first logic gate, said first enable signal INC_A and said second enable signal INC_B.

5. The method of claim 4 , further comprising:

providing a second logic gate comprising an output, wherein said flip-flop circuit comprises a first output Q, wherein an input of said second logic gate is electrically connected to said first output Q;

generating on an output of said second logic gate, said first status signal defining said first relationship on said output of said second logic gate.

6. The method of claim 5 , wherein said signal SIG_A=B comprises a logical low, and wherein said first status signal defining said first relationship is dependent upon said signal SIG_A=B comprising the logical low and logical state of said first enable signal INC_A and said second enable signal INC_B.

7. A computing system comprising a processor coupled to a computer-readable memory unit, said memory unit comprising a computer readable code configured to be executed by the processor to perform the method of claim 1 .

8. A process for supporting computer infrastructure, said process comprising providing at least one support service for at least one of creating, integrating, hosting, maintaining, and deploying computer-readable code in a computing system, wherein the code in combination with the computing system is capable of performing the method of claim 1 .

9. A computer program product, comprising a computer storage medium comprising a computer readable program code embodied therein, said computer readable program code configured to perform the method of claim 1 upon being executed by a processor of a computing system.

10. A method for forming an electrical circuit, comprising:

providing a first counter circuit, a second counter circuit, a flip-flop circuit, a logic circuit, a first OR gate, a second OR gate, and a first logic gate;

electrically connecting an output of said first counter circuit to a first input of said logic circuit;

electrically connecting an output of said second counter circuit to a second input of said logic circuit; and

electrically connecting an output of said logic circuit to an enable input E on said flip-flop circuit;

electrically connecting an output of said first logic gate to a data input D of said flip-flop;

electrically connecting an output of said first OR gate to an input PRE of the flip-flop circuit; and

electrically connecting an output said second OR gate to an input RST of the flip-flop circuit.

11. The method of claim 10 , further comprising:

providing a second logic gate, wherein said flip-flop circuit comprises a first output Q; and

electrically connecting an input of said second logic gate to said first output Q.

12. The method of claim 11 , further comprising:

providing a third logic gate, wherein said flip-flop circuit comprises a second output Q′; electrically connecting an input of said third logic gate to said second output Q′.

13. The method of claim 12 , wherein said first logic gate, said second logic gate, and said third logic gate each comprise an AND gate.