Thin film transistor and method of manufacturing the same
View Patent ↗A method of manufacturing a thin film transistor includes: forming an amorphous silicon layer and a blocking layer; forming a photoresist layer having first and second photoresist patterns spaced apart from each other on the blocking layer; etching the blocking layer using the first photoresist pattern as a mask to form first and second blocking patterns; reflowing the photoresist layer so the first and second photoresist patterns abut each other; forming a capping layer and a metal layer; removing the photoresist layer to expose the blocking layer and an offset region between the blocking layer and the metal layer; crystallizing the amorphous silicon layer by diffusing metals in the metal layer through the capping layer; etching the poly silicon layer using the first and second blocking patterns as a mask to form first and second semiconductor layers; and removing the first and second blocking patterns.
1. A method of manufacturing a thin film transistor, comprising:
a) forming an amorphous silicon layer on an insulating substrate;
b) forming a first photoresist layer on the amorphous silicon layer while exposing edge portions of the amorphous silicon layer;
c) forming a capping layer and a metal layer over an entire first surface of the insulating substrate;
d) removing the first photoresist layer to expose a portion of the amorphous silicon layer under the first photoresist layer;
e) crystallizing the amorphous silicon layer by diffusing metals in the metal layer through the capping layer into the amorphous silicon layer to form a poly silicon layer;
f) forming a second photoresist layer having first and second photoresist patterns on the poly silicon layer, wherein the first and second photoresist patterns are spaced apart from each other;
g) etching the poly silicon layer using the first and second photoresist patterns as a mask to form first and second semiconductor layers; and
h) removing the first and second photoresist patterns.
2. The method of claim 1 , wherein the metal layer is made of Ni or Pd and has a thickness of 1 Å to 5000 Å.
3. The method of claim 1 , wherein the capping layer is made of SiO2 or SiNx.
4. The method of claim 1 , further comprising surface-treating the first and the second semiconductor layers.
5. The method of claim 4 , wherein the surface treatment is performed using a dry-etching technique or an HF etching solution of 0.1% to 20%.
6. The method of claim 1 , wherein a high angle grain boundary formed in the step (e) is removed by etching process in the step (g).
7. The method of claim 1 , further comprising:
i) forming a gate insulating layer over the entire first surface of the insulating substrate;
j) forming a gate electrode on the gate insulating layer over the first and second semiconductor layers;
k) forming an interlayer insulating layer over the entire first surface of the insulating substrate;
l) etching the interlayer insulating layer to form contact holes; and
m) forming a source and drain electrode.
8. The method of claim 1 , wherein in the step (e), a portion of the amorphous silicon layer directly contacting the capping layer includes seeds, and the remaining portion of the amorphous silicon layer is crystallized through super grain silicon (SGS) so that a high-angle grain boundary exists on a portion of the poly silicon layer between first and second blocking patterns.
9. The method of claim 1 , further comprising: removing the capping layer and the metal layer.