Memory array of floating gate-based non-volatile memory cells
View Patent ↗A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
1. A method of programming a single bit in a memory cell of a memory array, the method comprising:
applying a first voltage to a word line, in a first set of word lines, connected to the memory cell to be programmed, wherein the memory cell is one of a plurality of memory cells organized in a matrix of rows and columns, each of the memory cells comprising:
an access transistor;
a floating gate memory transistor electrically connected to the access transistor; and
a coupling capacitor electrically connected to the memory transistor;
applying a second voltage to a word line, in a second set of word lines, connected to the memory cell to be programmed, the second voltage equal to the first voltage;
grounding a bit line, in a first set of bit lines, connected to the memory cell to be programmed;
applying a third voltage to a bit line, in a second set of bit lines, connected to the memory cell to be programmed, the third voltage being greater than the first voltage;
grounding bit lines, in the second set of bit lines, not connected to the memory cell to be programmed; and
grounding word lines, in the first set of word lines, not connected to the memory cell to be programmed.
2. The method of claim 1 , wherein each of the memory cells comprises a capacitor terminal electrically connected to the coupling capacitor, a program terminal electrically connected to the memory transistor, and a control terminal electrically connected to the access transistor.
3. The method of claim 1 , wherein:
the first set of word lines is electrically connected to the coupling capacitor in each of the memory cells in a respective row;
the second set of word lines is electrically connected to the access transistor in each of the memory cells in a respective row;
the first set of bit lines is electrically connected to the access transistor in each of the memory cells in a respective column; and
the second set of bit lines is electrically connected to the memory transistor in each of the memory cells in a respective column.
4. The method of claim 1 , wherein the memory array is organized in a two-dimensional array.
5. The method of claim 1 , wherein the programming is carried out by hot carrier programming.
6. The method of claim 1 , wherein the third voltage is sufficient to induce an impact ionization current at a drain of the memory transistor.
7. The method of claim 6 , wherein the impact ionization current generates energetic electrons and holes that create avalanche multiplication.
8. The method in claim 7 , wherein a positive voltage applied to the coupling capacitor creates an electric field that aids hot electron transport into the floating gate of the memory transistor.
9. The method of claim 1 , wherein the first and second voltages are each 5 volts.
10. The method of claim 1 , wherein the third voltage is greater than 5 volts and up to 15 volts.