Mask for forming a thin-film transistor, thin-film transistor substrate manufactured using the same and method of manufacturing a thin-film transistor substrate using the same
View Patent ↗A mask that is capable of forming a thin-film transistor (TFT) with improved electrical characteristics is presented. The mask includes a drain mask pattern, a source mask pattern and a light-adjusting pattern. The drain mask pattern blocks light for forming a drain electrode. The source mask pattern blocks light for forming a source electrode and faces the drain mask pattern. A distance between the drain and source mask patterns is no more than the resolution of an exposing device. The light-adjusting pattern is formed between end portions of the source mask pattern and the drain mask pattern to block at least some light from entering a space between the source and drain mask patterns.
1. A method of manufacturing a thin film transistor substrate, comprising:
forming a gate insulating layer, an active layer, a data metal layer and a photoresist film on a base substrate having a gate electrode to cover the gate electrode;
exposing the photoresist film using a mask to form a photoresist pattern having a channel groove, wherein the mask includes:
a drain mask pattern,
a source mask pattern spaced apart from the drain mask pattern and having a first side surface facing the drain mask pattern, and
a light-adjusting pattern interposed between two end portions of the source mask pattern and the drain mask pattern to prevent light from entering a channel region between the drain and source mask patterns from a transparent region surrounding the drain mask pattern, the source mask pattern and the channel region;
partially etching the data metal layer and the active layer using the photoresist pattern as an etching mask to form a data metal pattern and an active pattern;
decreasing a thickness of the photoresist pattern so that the data metal pattern is exposed through the channel groove; and
partially etching the data metal pattern through the channel groove to form a data line having a source electrode and a drain electrode.
2. The method of claim 1 , further comprising forming a pixel electrode electrically connected to the drain electrode.
3. The method of claim 1 , wherein the active pattern has substantially the same outline as the data line and the drain electrode except for a space between the source and drain electrodes, and
a side of the active pattern overlaps an imaginary line or extends beyond the imaginary line that is defined by two sides of the source electrode.
4. The method of claim 1 , wherein the distance between the drain and source mask patterns is about 2 μm to about 3 μm.
5. The method of claim 1 , wherein the light-adjusting pattern is spaced apart from each of the drain and source mask patterns by about 1 μm to about 2 μm.
6. The method of claim 1 , wherein a width of the light-adjusting pattern is about 1 μm to about 2 μm.
7. The method of claim 1 , wherein the source mask pattern has a U-shape surrounding a portion of the drain mask pattern.
8. The method of claim 1 , wherein the source mask pattern has a J-shape surrounding a portion of the drain mask pattern.
9. The method of claim 1 , wherein the source mask pattern extends substantially parallel to the drain mask pattern.
10. The method of claim 1 , wherein the light-adjusting pattern is connected to each of the end portions of the source mask pattern.
11. The method of claim 1 , wherein the light-adjusting pattern is connected to the drain mask pattern.
12. The method of claim 1 , wherein the light-adjusting pattern is interposed between each of the end portions of the source mask pattern and the drain mask pattern.
13. The method of claim 1 , wherein the light-adjusting pattern surrounds a portion of each of the end portions of the source mask pattern.
14. The method of claim 1 , wherein the light-adjusting pattern is disposed adjacent to a distal end of the first side surface.
15. The method of claim 13 , wherein the light-adjusting pattern has an L-shape.