LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

1 . A layout method for a semiconductor integrated circuit including a plurality of delay adjustment cells each of which adjusts a delay amount of a signal line, said layout method comprising:

placing the plurality of delay adjustment cells;

adjusting delay amounts of the plurality of delay adjustment cells placed in said placing;

extracting delay adjustment cells of a same kind from among the plurality of delay adjustment cells having the delay amounts adjusted in said adjusting; and

consolidating the delay adjustment cells of the same kind extracted in said extracting, to obtain a shared delay adjustment cell.

2 . The layout method for a semiconductor integrated circuit according to claim 1 , further comprising

re-placing the plurality of delay adjustment cells including the shared delay adjustment cell obtained in said consolidating, so as to reduce area of a region where the plurality of delay adjustment cells are placed.

3 . The layout method for a semiconductor integrated circuit according to claim 2 ,

wherein said re-placing includes aligning and re-placing the plurality of delay adjustment cells including the shared delay adjustment cell obtained in said consolidating, in an order depending on a size of the area of the delay adjustment cells.

4 . The layout method for a semiconductor integrated circuit according to claim 1 ,

wherein said placing includes placing an input-side logic cell and an output-side logic cell of the plurality of delay adjustment cells, so that the input-side logic cell and the output-side logic cell are respectively arranged on diagonally opposing sides of a region where the plurality of delay adjustment cells are placed.

5 . The layout method for a semiconductor integrated circuit according to claim 1 , further comprising

predicting the delay adjustment cells of the same kind from among the plurality of delay adjustment cells,

wherein said placing includes adjacently placing the delay adjustment cells of the same kind predicted in said predicting.

6 . The layout method for a semiconductor integrated circuit according to claim 1 ,

wherein said consolidating includes consolidating the delay adjustment cells of the same kind extracted in said extracting, to obtain one shared delay adjustment cell for every predetermined number or less of the delay adjustment cells.

7 . The layout method for a semiconductor integrated circuit according to claim 1 , further comprising:

dividing a region where the plurality of delay adjustment cells are placed in said placing into a plurality of re-placement target regions, and

wherein said extracting includes extracting the delay adjustment cells of the same kind from among the plurality of delay adjustment cells included in each of the re-placement target regions; and

said consolidating includes consolidating the delay adjustment cells of the same kind extracted in said extracting to obtain the shared delay adjustment cell, for each of the re-placement target regions.

8 . A program which causes a computer to execute a layout method for a semiconductor integrated circuit including a plurality of delay adjustment cells each of which adjusts a delay amount of a signal line,

the method includes:

placing the plurality of delay adjustment cells;

adjusting delay amounts of the plurality of delay adjustment cells placed in said placing;

extracting delay adjustment cells of a same kind from among the plurality of delay adjustment cells having the delay amounts adjusted in said adjusting; and

consolidating the delay adjustment cells of the same kind extracted in said extracting, to obtain a shared delay adjustment cell.

9 . A semiconductor integrated circuit comprising:

a delay adjustment cell having an input connected to a clock terminal and which imparts a predetermined delay to an inputted signal and output the signal;

a plurality of selectors each of which selects one of the signal outputted by the delay adjustment cell and a signal from a test terminal, and outputs the signal; and

a plurality of flip-flops each of which has a clock input terminal to which the signal outputted by one of said plurality of selectors is inputted.