Central processor for a camera with printing capabilities
View Patent ↗A central processor for a camera having printing capabilities has a CPU core. A data cache is connected to the core. A vector processor is connected to the core via the data cache. A RAM interface is connected to the data cache to permit communication with a RAM. An input buffer is connected to the processor. An image sensor interface is connected to the input buffer for communication with the processor. A card reader interface is connected to the input buffer for communication with the processor. An output buffer is connected to the processor. A printhead interface is connected to the output buffer for communication with the processor.
1. A central processor for a camera having printing capabilities, the central processor comprising
a CPU core;
a data cache connected to the core;
a vector processor connected to the core via the data cache;
a RAM interface connected to the data cache to permit communication with a RAM;
an input buffer connected to the processor;
an image sensor interface connected to the input buffer for communication with the processor;
a card reader interface connected to the input buffer for communication with the processor;
an output buffer connected to the processor; and
a printhead interface connected to the output buffer for communication with the processor.
2. A processor as claimed in claim 1 , in which the CPU core is a RISC core.
3. A processor as claimed in claim 2 , in which the CPU core is a 32 bit RISC core configured to run an image processing language and to perform general operating system duties of the camera.
4. A processor as claimed in claim 1 , in which the data cache is configured to have a minimum of 16 cache lines.
5. A processor as claimed in claim 1 , in which the RAM interface is a direct RAM interface.
6. A processor as claimed in claim 1 , in which the vector processor is a four-way parallel VLIW vector processor.
7. A processor as claimed in claim 1 , in which the input and output buffers are 8-bit wide FIFO buffers.
8. A processor as claimed in claim 1 , in which the card reader interface is configured to receive image processing instructions carried on a card.
9. A processor as claimed in claim 1 , in which the printhead interface is configured to communicate print data to a pagewidth inkjet printhead.