Method and tester for verifying the electrical connection integrity of a component to a substrate

1. A method for verifying the integrity of the electrical connection between at least one signal path of a substrate and at least one respective contact of a component mounted on the substrate, the method comprising:

generating a step signal on one of the at least one signal path connected to a respective contact;

capturing a capacitively coupled signal due to the step signal at the contact; and

determining the integrity of the electrical connection from a characteristic of one of the capacitively coupled signal and a response signal obtained from the capacitively coupled signal.

2. A method according to claim 1 , wherein the method further comprises obtaining the response signal from the capacitively coupled signal, and wherein determining the integrity of the electrical connection comprises determining the integrity of the electrical connection from a characteristic of the response signal.

3. A method according to claim 2 , wherein obtaining the response signal from the capacitively coupled signal comprises obtaining one of an under-damped, an over-damped and a critically-damped signal from the capacitively coupled signal.

4. A method according to claim 2 , wherein determining the integrity of the electrical connection from a characteristic of the response signal comprises determining the integrity of the electrical connection from one of an amplitude, a phase, a timing and a frequency of the response signal.

5. A method according to claim 2 , wherein determining the integrity of the electrical connection from a characteristic of the response signal comprises:

digitizing the response signal to obtain samples thereof;

performing digital signal processing on the samples to obtain the characteristic of the response signal.

6. A method according to claim 5 , wherein performing digital signal processing on the samples comprises one of:

carrying out Discrete Fourier Transform on the samples;

carrying out Fast Fourier Transform on the samples; and

filtering the samples using a digital filter.

7. A method according to claim 2 , wherein the method further comprises putting a second contact adjacent to the first contact to a state that disrupts the step signal at the first contact if the two contacts are shorted.

8. A method according to claim 2 , wherein the at least one contact of the component comprises at least two contacts of the component, and wherein

generating a step signal on the signal path comprises generating a step signal simultaneously on each signal path;

capturing a capacitively coupled signal comprises capturing a capacitively coupled signal due to the simultaneously generated step signals; and

determining the integrity of the electrical connection comprises determining the integrity of all the electrical connections from a characteristic of the response signal.

9. A method according to claim 2 , wherein the at least one contact of the component comprises at least two contacts of the component, and wherein

generating a step signal on the signal path comprises generating a step signal in sequence on each signal path;

capturing a capacitively coupled signal comprises capturing a capacitively coupled signal having a respective signal portion due to each step signal; and

determining the integrity of the electrical connection comprises determining the integrity of the electrical connection of each contact from a characteristic of the corresponding signal portion of the response signal.

10. A method according to claim 2 , wherein the at least one contact of the component comprises at least two contacts of the component, and wherein

generating a step signal on the signal path comprises generating a first step signal on the signal path connected to one contact and a second step signal on the signal path connected to another contact simultaneously; the first step signal and the second step signal being of opposite polarity; and

capturing a capacitively coupled signal comprises capturing a capacitively coupled signal due to the simultaneously generated step signals.

11. A method according to claim 10 , wherein capturing a capacitively coupled signal due to the simultaneously generated step signals comprises capturing a capacitively coupled signal due to the simultaneously generated step signals differentially.

12. A method according to claim 2 , wherein the at least one contact of the component comprises at least two contacts of the component, and wherein

generating a step signal on the signal path comprises generating a first step signal on the signal path connected to one contact and a second step signal on the signal path connected to another contact simultaneously; the first step signal and the second step signal being of opposite polarity; and

capturing a capacitively coupled signal comprises capturing a capacitively coupled signal due to only one of the two simultaneously generated step signals.

13. A method according to claim 2 , wherein obtaining the response signal from the capacitively coupled signal comprises processing the captured capacitively coupled signal according to a characteristic of a capacitive sensor that is used to capture the capacitively coupled signal.

14. A method according to claim 13 , wherein processing the captured capacitively coupled signal according to a characteristic of a capacitive sensor comprises at least one of amplifying and digital signal processing the captured capacitively coupled signal according to a characteristic of the capacitive sensor.

15. A method according to claim 1 , wherein generating a step signal on one of the at least one signal path comprises controlling a boundary scan (BSCAN) device to generate the step signal.

16. A method according to claim 1 , wherein the method further comprises coordinating the generating of the step signal and the capturing of the capacitively coupled signal via a trigger signal.

17. A method according to claim 1 , wherein the at least one signal path is pulled high, pulled low or pulled to a fixed voltage level, and wherein generating a step signal on one of the at least one signal path comprises putting the signal path from a logic level high or low to a tri-state state.

18. A tester for verifying the integrity of the electrical connection between at least one signal path of a substrate and at least one respective contact of a component mounted on the substrate, the tester comprising:

means for receiving a signal due to a step signal applied to one of the at least one signal path connected to a respective contact, the signal being one of a capacitively coupled signal and a response signal obtained from the capacitively coupled signal; and

means for determining the integrity of the electrical connection from a characteristic of the signal.

19. A tester according to claim 18 , further comprising means for generating the step signal on the signal path.

20. A tester according to claim 19 , wherein the means for generating the step signal comprises a means for controlling a BSCAN device to generate the step signal.

21. A tester according to claim 18 , wherein the means for receiving the signal comprises a means for receiving the signal upon the receipt of a trigger signal indicating the generation of the step signal on the signal path.

22. A tester according to claim 18 further comprises means for obtaining the response signal from the capacitively coupled signal, and wherein the means for determining the integrity of the electrical connection from a characteristic of the signal comprises a means for determining the integrity of the electrical connection from a characteristic of the response signal.

23. A tester according to claim 22 , wherein means for obtaining the response signal from the capacitively coupled signal comprises a means for obtaining one of an under-damped, an over-damped and a critically-damped signal from the capacitively coupled signal.

24. A tester according to claim 22 , further comprising a capacitive sensor that captures the capacitively coupled signal, and wherein the means for obtaining the response signal from the capacitively coupled signal comprises a means for processing the captured capacitively coupled signal according to a characteristic of the capacitive sensor.

25. A tester according to claim 24 , wherein the means for processing the captured capacitively coupled signal according to a characteristic of a capacitive sensor comprises at least one of a means for amplifying the captured capacitively coupled signal according to a characteristic of the capacitive sensor and a means for carrying out digital signal processing on the captured capacitively coupled signal according to the characteristic of the capacitive sensor.