IP Library Granted Patent US 7,875,958
Granted Patent B2
US 7,875,958 · App. 11/862,850 · Granted Jan 25, 2011

Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 7,875,958
App. No.
11/862,850
Granted
Jan 25, 2011
Kind
B2
Abstract

Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Claims (22)

1. A structure comprising:

a non-crystalline material defining an opening having a sidewall disposed above a surface of a substrate, the substrate comprising a first crystalline semiconductor material;

a second crystalline semiconductor material disposed in the opening, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material, and the second crystalline semiconductor material having a height equal to or greater than half a width of the opening, wherein the height is in a direction orthogonal to the surface of the substrate, and the width is in a direction parallel to the surface of the substrate; and

a tunneling device disposed over at least a portion of the second crystalline semiconductor material.

2. The structure of claim 1 , wherein the tunneling device is selected from the group consisting of an Esaki diode (tunnel diode), a single-barrier tunnel diode, a resonant tunneling diode (RTD), a triple-barrier or multiple-barrier resonant tunneling diode, a resonant interband tunneling diode (RITD), a single-barrier interband-tunneling diode, a resonant tunneling transistor (RTT), a resonant tunneling field-effect transistor (RTFET), a double electron layer tunnel transistor (DELTT), a quantum-well-based resonant tunneling transistor (QWBRTT), a resonant tunneling bipolar transistor (RTBT or RBT), and a resonant tunneling hot-electron transistor (RHET).

3. The structure of claim 1 , further comprising a phase change layer disposed over the tunneling device, wherein the structure comprises a memory cell.

4. The structure of claim 1 , further comprising a ferroelectric material disposed over the tunneling device, wherein the structure comprises a memory cell.

5. The structure of claim 1 , further comprising memory circuitry, wherein the memory circuitry includes the tunneling device.

6. The structure of claim 5 , wherein the memory circuitry comprises at least one of SRAM circuitry, DRAM circuitry, or non-volatile memory circuitry.

7. The structure of claim 1 , wherein the first crystalline semiconductor material comprises at least one of a group IV element or compound, a II-VI compound, or a III-V compound, the second crystalline material comprises at least one of a group IV element or compound, a II-VI compound or a III-V compound, and the first crystalline semiconductor material and the second crystalline semiconductor material comprise materials selected from different groups.

8. The structure of claim 1 wherein a majority of defects arising from the lattice-mismatch of the first and second crystalline semiconductor materials terminate within the opening.

9. The structure of claim 1 wherein a majority of defects arising from the lattice-mismatch of the first and second crystalline semiconductor materials terminate below a height of the opening.

10. The structure of claim 1 wherein the width of the opening is less than a height of the opening.

11. The structure of claim 1 wherein the tunneling device is in contact with at least a portion of the second crystalline material.

12. The structure of claim 1 , further comprising a circuit component coupled to the tunneling device and disposed above a region of the substrate.

13. The structure of claim 12 wherein the circuit component comprises at least one of a MOSFET, a MISFET, a HEMT, a capacitor, or a resistor.

14. The structure of claim 12 , wherein the circuit component comprises at least one of a gate array, a memory circuit, or a processor circuit.

15. The structure of claim 1 , wherein the tunneling device comprises a tunneling diode disposed above a transistor.

16. The structure of claim 1 , wherein the tunneling diode is disposed above a source or drain of a transistor.

17. The structure of claim 16 , further comprising a second tunneling diode disposed over the source or drain of the transistor.

18. The structure of claim 1 , wherein the second crystalline semiconductor material adjoins the first crystalline semiconductor material.

19. The structure of claim 1 , wherein substantially all defects in the second crystalline semiconductor material terminated at sidewalls of the opening.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2010
From: AMBERWAVE SYSTEMS CORPORATION
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 023775/0111 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2008
From: CHENG, ZHIYUAN; SHEEN, CALVIN
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 021072/0718 →
Continuity (3)
Provisional Application 6084803700 · Sep 27, 2006
Provisional Application 6092383800 · Apr 17, 2007
Related Publication 20080073641A1 · Mar 27, 2008