H.264 video decoder CABAC core optimization techniques
A device employing techniques to optimize Context-based Adaptive Binary Arithmetic Coding (CABAC) for the H.264 video decoding is provided. The device includes a processing circuit operative to implement a set of instructions to decode multiple bins simultaneously and renormalize an offset register and a range register after the multiple bins are decoded. The range register and offset registers may be 32 or 64 bits. The use of a larger range register allows renormalization to be skipped when enough bits are still in the range register.
1. A device comprising:
a processing circuit operative to implement a set of instructions to decode multiple bins simultaneously and renormalize an offset register and a range register, wherein the renormalization occurs in intervals of bytes, and wherein renormalizing the offset register and the range register comprises a first type of renormalization process employed by a bypass decoding mode process and a second type of renormalization process employed, after normal decoding, by a normal decoding mode process, wherein the first type of renormalization process comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a first threshold, and wherein the second type of renormalization process comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a second threshold; and
a memory coupled to the processing circuit.
2. The device according to claim 1 , wherein the set of instructions to renormalize includes count leading zero instructions to calculate an amount of left shift needed to multi-bit align the range register and the offset register.
3. The device according to claim 1 , wherein the multiple bins are represented in an exponent Golomb binarization (EG) code.
4. The device according to claim 1 , wherein the set of instructions to decode multiple bins includes instructions to decode up to 16 consecutive bins simultaneously.
5. The device according to claim 1 , wherein the set of instructions to decode multiple bins is configured to decode context-adaptive binary arithmetic coding (CABAC).
6. The device according to claim 5 , wherein the processing circuit further comprises instructions to decode two consecutive normal mode symbols simultaneously.
7. The device according to claim 1 , wherein the device comprises a cellular phone, wireless device, wireless communications device, a video game console, a wirelessly-equipped personal digital assistant (PDA), a laptop computer, or a video-enabled device.
8. A device comprising:
decoding means for decoding multiple bins simultaneously; and
renormalizing means for multi-bit aligning an offset register and a range register in intervals of bytes, wherein the renormalizing means comprises a first type of renormalizing means employed by a bypass decoding mode process means and a second type of renormalizing means employed, after normal decoding, by a normal decoding mode process means, wherein the first type of renormalizing means comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a first threshold, and wherein the second type of renormalization process comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a second threshold.
9. The device according to claim 8 , wherein the renormalizing means includes calculating means for calculating an amount of left shift needed to multi-bit align the range.
10. The device according to claim 8 , wherein the decoding means includes means for decoding an exponent Golomb binarization (EG) code.
11. The device according to claim 8 , wherein decoding means comprises means for decoding context-adaptive binary arithmetic coding (CABAC).
12. The device according to claim 11 , wherein the decoding means includes means for decoding two consecutive normal mode symbols simultaneously.
13. An apparatus comprising:
a decoder having an offset register and a range register and which decodes multiple bins simultaneously and renormalizes the offset register and the range register, wherein renormalization occurs in intervals of bytes, and wherein the renormalizing the offset register and the range register comprises a first type of renormalization process employed by a bypass decoding mode process and a second type of renormalization process employed, after normal decoding, by a normal decoding mode process, wherein the first type of renormalization process comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a first threshold, and wherein the second type of renormalization process comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a second threshold; and
a memory coupled to the decoder.
14. The apparatus according to claim 13 , wherein the decoder calculates an amount of left shift needed to multi-bit align the range register and the offset register.
15. The apparatus according to claim 13 , wherein the decoder decodes an exponent Golomb binarization (EG) code.
16. A computer program product including a non-transitory computer readable storage medium having instructions for causing a computer to:
decode multiple bins simultaneously; and
renormalize for multi-bit aligning an offset register and a range register in intervals of bytes, wherein renormalizing the offset register and the range register comprises a first type of renormalization process employed by a bypass decoding mode process and a second type of renormalization process employed, after normal decoding, by a normal decoding mode process, wherein the first type of renormalization process comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a first threshold, and wherein the second type of renormalization process comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a second threshold.
17. The computer program product according to claim 16 , wherein the instructions to renormalize includes instructions to calculate an amount of left shift needed to multi-bit align the range register and the offset register.
18. The computer program product according to claim 16 , wherein the instructions to decode include instruction to decode an exponent Golomb binarization (EG) code.
19. The computer program product according to claim 16 , wherein the instructions to decode include instructions to decode context-adaptive binary arithmetic coding (CABAC).
20. A method comprising
decoding multiple bins simultaneously; and
renormalizing for multi-bit aligning an offset register and a range register in intervals of bytes, wherein the renormalizing comprises a first type of renormalization process employed by a bypass decoding mode process and a second type of renormalization process employed, after normal decoding, by a normal decoding mode process, wherein the first type of renormalization process comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a first threshold, and wherein the second type of renormalization process comprises shifting the range register and the offset register by multiple bytes based on whether the range register is less than a second threshold;
wherein the method is performed in an electronic unit.
21. The method according to claim 20 , wherein the renormalizing includes calculating an amount of left shift needed to multi-bit align the range register and the offset register.
22. The method according to claim 21 , wherein the decoding includes decoding an exponent Golomb binarization (EG) code.
23. The method according to claim 21 , wherein the decoding includes decoding context-adaptive binary arithmetic coding (CABAC).