Systems and methods for reduced complexity LDPC decoding
View Patent ↗Systems and methods for generating check node updates in the decoding of low-density parity-check (LDPC) codes use new approximations in order to reduce the complexity of implementing a LDPC decoder, while maintaining accuracy. The new approximations approximate the standard float-point sum-product algorithm (SPA), and can reduce the approximation error of min-sum algorithm (MSA) and have almost the same performance under 5 bits fix-point realization as the float-point sum-product algorithm (SPA).
1. A receiver, comprising:
a demodulator configured to receive a wireless signal comprising an original data signal and a carrier signal, remove the carrier signal from the wireless signal, and produce a received signal; and
a Low Density Parity Check (LDPC) processor coupled with the demodulator, the LDPC processor configured to recover the original data signal from the received signal, the LDPC processor comprising:
a plurality of variable node processors configured to generate variable messages based on the received signal, and
a check node processor coupled with the plurality of variable node processors, the check node processor configured to implement an approximation of a sum product algorithm (SPA) using base 2 logarithm operations and rounding all operands and results to the nearest integer.
2. The receiver of claim 1 , wherein the check node processor is further configured to implement an approximation of a sum product algorithm (SPA) which is equivalent to:
x
⊕
y
≈
sign
(
x
)
sign
(
y
)
[
min
(
x
,
y
)
-
ɛ
(
x
,
y
)
]
where
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(
a
,
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=
{
1
a
-
b
≤
1
and
min
(
a
,
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)
>
1
0
else
.
3. The receiver of claim 1 , wherein the check node processor comprises binary hardware circuits.
4. The receiver of claim 1 , wherein the integers produced are limited to within ±A max =±(2 v−1 −1).
5. The receiver of claim 4 , wherein the check node processor comprises v fixed point circuits including 1 bit for the signs of the integers and v−1 bits for the absolute value.
6. The receiver of claim 1 , wherein the LDPC processor is implemented in a single processor.
7. The receiver of claim 1 , wherein the received signal is modulated using any combination of the following techniques:
Bi-Phase Shift Keying (PBSK);
Quadrature Phase Shift Keying (QPSK); and
Quadrature Amplitude Modulation (QAM).
8. A Low Density Parity Check (LDPC) processor, comprising:
a plurality of variable node processors configured to generate variable messages based on the received signal, and
a check node processor coupled with the plurality of variable node processors, the check node processor configured to implement an approximation of a sum product algorithm (SPA) using base 2 logarithm operations and rounding all operands and results to the nearest integer.
9. The LDPC processor of claim 8 , wherein the check node processor is further configured to implement an approximation of a sum product algorithm (SPA) which is equivalent to
x
⊕
y
≈
sign
(
x
)
sign
(
y
)
[
min
(
x
,
y
)
-
ɛ
(
x
,
y
)
]
where
ɛ
(
a
,
b
)
=
{
1
a
-
b
≤
1
and
min
(
a
,
b
)
>
1
0
else
.
10. The LDPC processor of claim 9 , wherein the integers produced are limited to within ±A max =±(2 v−1 −1).
11. The receiver of claim 10 , wherein the check node processor comprises v fixed point circuits including 1 bit for the signs of the integers and v−1 bits for the absolute value.
12. The LDPC processor of claim 8 , wherein the check node processor comprises binary hardware circuits.
13. A method for processing a received signal using a parity node processor included in a LDPC decoder, the method comprising:
receiving a signal;
demodulating the signal;
generating a variable message; and
generating a soft output based on the variable message using an approximation of a sum product algorithm (SPA) using base 2 logarithm operations and rounding all operands and results to the nearest integer.
14. The method of claim 13 , further comprising refining the soft output variable message iteratively until either the soft output variable message matches a parity node equation or a maximum number of iterations has occurred.
15. The method of claim 13 , wherein the soft output generated is equivalent to:
x
⊕
y
≈
sign
(
x
)
sign
(
y
)
[
min
(
x
,
y
)
-
ɛ
(
x
,
y
)
]
where
ɛ
(
a
,
b
)
=
{
1
a
-
b
≤
1
and
min
(
a
,
b
)
>
1
0
else
.
16. The method of claim 13 , wherein the integers produced are limited to within ±A max =±(2 v−1 −1).
17. The method of claim 13 , wherein the signal is modulated using any combination of the following techniques:
Bi-Phase Shift Keying (PBSK);
Quadrature Phase Shift Keying (QPSK); and
Quadrature Amplitude Modulation (QAM).