Display driving chip
View Patent ↗Disclosed is a display driving chip of a semiconductor chip. According to an embodiment, the display driving chip comprises, input/output (I/O) pads each electrically connected to a lower interconnection on an active area, the I/O pads forming a perimeter on an inner peripheral surface of the active area, and dummy pads formed on the active area within the perimeter of I/O pads.
1. A display driving chip, comprising:
input/output (I/O) pads each electrically connected to a lower interconnection on an active area, wherein the I/O pads form a perimeter on an inner peripheral surface of the active area; and
dummy pads on the active area within an inner peripheral surface of the perimeter of I/O pads.
2. The display driving chip according to claim 1 , wherein the dummy pads are not electrically connected to the lower interconnections on the active area.
3. The display driving chip according to claim 1 , wherein the I/O pads and the dummy pads each have a dual structure comprising a first metal pad and a second metal pad.
4. The display driving chip according to claim 1 , wherein an interval between each I/O pad and each dummy pad is in a range of 10 λm to 500 μm.
5. The display driving chip according to claim 1 , wherein the I/O pads each comprise:
a first metal pad connected to the lower interconnection on a semiconductor substrate;
at least one via on the first metal pad; and
a second metal pad on the via.
6. The display driving chip according to claim 5 , wherein the at least one via has a Y shape.
7. The display driving chip according to claim 6 , wherein the at least one via has a height of 0.1 μm to 20 μm between the first metal pad and the second metal pad.
8. The display driving chip according to claim 6 , wherein the length of one branch of the at least one Y-shaped via is 0.1 μm to 100 μm.
9. The display driving chip according to claim 5 , wherein the at least one via comprises Cu, AlCu, W, Ti, Ta or Co.
10. The display driving chip according to claim 5 , wherein the at least one via has an area ratio of 1% to 80% with respect to an area of the first and second metal pads.
11. The display driving chip according to claim 1 , wherein the dummy pad comprises:
a first metal pad on an interlayer dielectric layer on a semiconductor substrate;
at least one via on the first metal pad; and
a second metal pad on the via.
12. The display driving chip according to claim 11 , wherein the at least one via has a Y shape.
13. The display driving chip according to claim 12 , wherein the at least one via has a height of 0.1 μm to 20 μm between the first metal pad and the second metal pad.
14. The display driving chip according to claim 12 , wherein the length of one branch of the at least one Y-shaped via is 0.1 μm to 100 μm.
15. The display driving chip according to claim 11 , wherein the at least one via comprises Cu, AlCu, W, Ti, Ta or Co.
16. The display driving chip according to claim 11 , wherein the at least one via has an area ratio of 1% to 80% with respect to an area of the first and second metal pads.
17. The display driving chip according to claim 1 , wherein the I/O pads and the dummy pads each comprise Cu, AlCu, W, Ti, Ta or Co.