Inverted doherty amplifier with increased off-state impedence
View Patent ↗An amplifier that amplifies an input signal and provides the amplified signal to a load at a summing junction that has a first impedance value. The amplifier includes a splitter network receiving the input signal and providing a phase delayed signal and an undelayed signal; a carrier amplifier path amplifying the phase delayed signal and including a carrier amplifier and a first output match network coupled between the carrier amplifier and the summing node; and a peaking amplifier path amplifying the undelayed signal and including a peaking amplifier, a second output match network coupled to the peaking amplifier, and a phase delay element coupled between the second output match network and the summing node, wherein the phase delay element provides a degree of phase delay and has a designed characteristic impedance value that is larger than the first impedance value for increasing the off-state impedance of the peaking amplifier.
1. A power amplifier for amplifying an input signal and providing an amplified signal to a load at a summing node, wherein the load has a first impedance value, the power amplifier comprising:
a splitter network receiving the input signal and providing a phase delayed signal and an undelayed signal, wherein the phase delayed signal is delayed by substantially a first predetermined degree of phase delay with respect to the undelayed signal;
a carrier amplifier path amplifying the phase delayed signal and comprising a carrier amplifier and a first output match network coupled between the carrier amplifier and the summing node; and
a peaking amplifier path amplifying the undelayed signal and comprising a peaking amplifier, a second output match network coupled to the peaking amplifier, and a phase delay element coupled between the second output match network and the summing node, wherein the phase delay element provides substantially the first predetermined degree of phase delay and has a designed characteristic impedance value that is larger than the first impedance value for increasing the off-state impedance of the peaking amplifier based on the designed characteristic impedance value, when the peaking amplifier is off.
2. The power amplifier of claim 1 , wherein the first impedance value is substantially 50 Ohms and the designed characteristic impedance value of the phase delay element is greater than 50 Ohms.
3. The power amplifier of claim 2 , wherein the designed characteristic impedance value of the phase delay element is substantially 75 Ohms.
4. The power amplifier of claim 1 , wherein the carrier amplifier and the peaking amplifier each comprise a laterally diffused metal oxide field effect transistor.
5. The power amplifier of claim 1 , wherein the power amplifier is included in at least one of a base transceiver station and a mobile device.
6. The power amplifier of claim 1 , wherein the second output match network is configured based on the designed characteristic impedance value of the phase delay element.
7. The method of claim 1 , wherein the phase delay element is substantially a quarter wavelength element.
8. The method of claim 1 , wherein the first predetermined degree of phase delay is 90 degrees of phase delay.
9. A power amplifier for amplifying an input signal and providing an amplified signal to a load at a summing node, wherein the load has a first impedance value, the power amplifier comprising:
a splitter network receiving the input signal and providing a phase delayed signal and an undelayed signal, wherein the phase delayed signal is delayed by substantially 90 degrees with respect to the undelayed signal;
a carrier amplifier path amplifying the phase delayed signal and comprising a carrier amplifier and a first output match network coupled between the carrier amplifier and the summing node; and
a peaking amplifier path amplifying the undelayed signal and comprising a peaking amplifier, a second output match network coupled to the peaking amplifier, and a phase delay element coupled between the second output match network and the summing node, wherein the phase delay element provides substantially 90 degrees of phase delay and has a designed characteristic impedance value that is larger than the first impedance value for increasing the off-state impedance of the peaking amplifier based on the designed characteristic impedance value, when the peaking amplifier is off.