Electron multiplication CMOS imager

1. A pixel for an imager, comprising:

at least one electron multiplication (EM) gain stage configured in a loop and electrically coupled to a charge collection region and a charge readout region, said charge collection region being configured to generate a charge packet, said EM gain stage being configured to amplify the charge packet by impact ionization and to circulate the charge packet a predetermined number of times in one direction around said loop, said charge readout region being configured to receive the amplified charge packet and convert the amplified charge to a measurable signal,

wherein said at least one EM gain stage comprises:

a first clocked gate,

a second clocked gate,

a DC gate formed between said first clocked gate and said second clocked gate, and

a second DC gate formed proximal to said first clocked gate and distal to said second clocked gate,

wherein said first DC gate and said second DC gate are combined with a step potential profile under said first clocked gate and said second clocked gate so as to set a direction of flow of the charge packet around said loop.

2. The pixel of claim 1 , wherein said at least one EM gain stage, said charge collection region, and said charge readout region are formed monolithically in an integrated circuit.

3. The pixel of claim 1 ,

wherein when a first voltage is applied to said first clocked gate, a first charge well is formed below said first clocked gate; when a second voltage greater than the first voltage is applied to said second clocked gate, a second charge well that is deeper than said first charge well is formed below said second clocked gate; when a DC voltage less than the first and second voltages is applied to the DC gate, a charge barrier is formed between said first charge well and said second charge well; and when a third potential is applied to said first clocked gate that is less than said DC voltage, the charge packet undergoes impact ionization as it transfers from said first charge well to said second charge well.

4. The pixel of claim 2 , wherein said integrated circuit is manufactured using a CMOS process.

5. The pixel of claim 2 , further comprising a second EM gain stage formed in said integrated circuit with said first EM gain stage in a loop.

6. The pixel of claim 1 , wherein said charge collection region further comprises one of a pinned photodiode (PPD), a photogate, and a conventional photodiode.

7. The pixel of claim 1 , wherein said charge readout region further comprises a floating diffusion sense node and a transfer gate for transferring the charge packet from said EM gain stage to said floating diffusion sense node.

8. The pixel of claim 7 , wherein said readout structure further comprises:

a source follower transistor electrically connected to said floating diffusion sense node;

a row select gate electrically connected to said source follower transistor; and

a source follower reset gate electrically connected to said source follower transistor.

9. The pixel of claim 1 , wherein an optically opaque shield is placed substantially overlying said EM gain stage and said charge readout region.

10. The pixel of claim 9 , further comprising a color filter placed substantially overlying said charge collection region.

11. The pixel of claim 9 , further comprising a microlens placed substantially overlying said charge collection region.

12. The pixel of claim 1 , further comprising a substrate substantially underlying the EM gain stage and said charge readout region, said EM gain stage and said charge readout region being placed in a doped well of higher doping than the substrate doping.

13. The pixel of claim 12 , further comprising a color filter placed substantially underlying said substrate.

14. The pixel of claim 12 , further comprising a microlens placed substantially underlying said substrate.

15. An imaging array, comprising:

a plurality of pixels, each pixel comprising:

at least one electron multiplication (EM) gain stage configured in a loop and electrically coupled to a charge collection region and a charge readout region, said charge collection region being configured to generate a charge packet, said EM gain stage being configured to amplify the charge packet by impact ionization and to circulate the charge packet a predetermined number of times in one direction around said loop, said charge readout region being configured to receive the amplified charge packet and convert the amplified charge to a measurable signal,

wherein said at least one EM gain stage comprises:

a first clocked gate,

a second clocked gate,

a DC gate formed between said first clocked gate and said second clocked gate, and

a second DC gate formed proximal to said first clocked gate and distal to said second clocked gate,

wherein said first DC gate and said second DC gate are combined with a step potential profile under said first clocked gate and said second clocked gate so as to set a direction of flow of the charge packet around said loop;

at least one row selection line coupled to at least one charge readout region; and

at least one amplifier for receiving and amplifying the measurable signal from said at least one charge readout region selected by said at least one row selection line.

16. The imaging array of claim 15 , wherein said at least one EM gain stage, said charge collection region, and said charge readout region are formed monolithically in an integrated circuit.

17. The imaging array of claim 15 , further comprising:

a column select multiplexer coupled to said at least one charge readout region; and

an output buffer coupled to said column select multiplexer.

18. The imaging array of claim 15 ,

wherein when a first voltage is applied to said first clocked gate, a first charge well is formed below said first clocked gate; when a second voltage greater than the first voltage is applied to said second clocked gate, a second charge well that is deeper than said first charge well is formed below said second clocked gate; when a DC voltage less than the first and second voltages is applied to the DC gate, a charge barrier is formed between said first charge well and said second charge well; and when a third potential is applied to said first clocked gate that is less than said DC voltage, the charge packet undergoes impact ionization as it transfers from said first charge well to said second charge well.

19. The imaging array of claim 15 , wherein said plurality of pixels is manufactured using a CMOS process.

20. The imaging array of claim 15 , wherein each of said pixels further comprises a second EM gain stage formed with said first EM gain stage in a loop.

21. The imaging array of claim 15 , wherein said charge collection region further comprises one of a pinned photodiode (PPD), a photogate, and a conventional photodiode.

22. The imaging array of claim 15 , wherein said charge readout region further comprises a floating diffusion sense node and a transfer gate for transferring the charge packet from said EM gain stage to said floating diffusion sense node.

23. The imaging array of claim 15 , wherein said charge readout region further comprises:

a source follower transistor electrically connected to said floating diffusion sense node;

a row select gate electrically connected to said source follower transistor; and

a source follower reset gate electrically connected to said source follower transistor.