Coupling device for transmitting data

1. A coupling device for coupling a memory, which has a serial data output, with a processor, which has a parallel data input, the coupling device comprising:

a serial data interface configured to receive data;

a parallel data interface configured to transmit data;

a cache memory coupled to the serial data interface and to the parallel data interface, wherein the cache memory is configured to receive and store data, which have been received in a serial data format via the serial data interface, and to transmit data stored in the cache memory to the parallel data interface; and

a buffer memory, which is coupled with the serial data interface and with the parallel data interface, wherein the buffer memory is configured to store data, which the serial data interface has received, and to output data which are stored in the buffer memory, to the parallel data interface.

2. The coupling device of claim 1 ,

wherein the parallel data interface is further configured to receive data.

3. The coupling device of claim 2 ,

wherein the parallel data interface is further configured to receive instruction data specifying which data should be transmitted by the parallel data interface.

4. The coupling device of claim 3 ,

wherein the parallel data interface comprises a parallel data bus and a parallel address bus.

5. The coupling device of claim 1 ,

wherein the serial data interface is further configured to transmit data.

6. The coupling device of claim 5 ,

wherein the serial data interface is further configured to transmit instruction data specifying which data should be read from a memory and should be received by the parallel data interface.

7. The coupling device of claim 2 ,

wherein the cache memory is configured to receive data, which the parallel data interface has received, and to output the received data to the serial data interface.

8. A coupling device for coupling a memory, which has a serial data output, with a processor, which has a parallel data input, the coupling device comprising:

a serial data interface configured to receive data;

a parallel data interface configured to transmit data; and

a cache memory coupled to the serial data interface and to the parallel data interface, wherein the cache memory is configured to receive and store data, which have been received in a serial data format via the serial data interface, and to transmit data stored in the cache memory to the parallel data interface,

wherein the cache memory is further configured to check as to whether data, which are requested by means of instruction data received by means of the parallel data interface, are stored in the cache memory, and, in case that the requested data are stored in the cache memory, to directly output the stored data to the parallel data interface, and, in case that the requested data are not stored in the cache memory, to cause the serial data interface to transmit instruction data, which specify that the requested data should be read from a memory and should be received by the serial data interface.

9. The coupling device of claim 8 ,

wherein the cache memory is further configured to, in case that the requested data are not stored in the cache memory, cause the serial data interface to transmit instruction data, which specify that a data amount that is larger than the requested data and which comprises the requested data, should be read from a memory and should be received by the serial data interface.

10. The coupling device of claim 9 ,

wherein the data amount is at least so large that it can fill a memory row of the cache memory.

11. The coupling device of claim 8 ,

wherein the requested data comprise instruction code which should be received by a processor, which has a parallel data interface, by means of the parallel data interface, and which should directly be executed by the processor.

12. A processor arrangement, comprising:

a coupling device for coupling a memory, which has a serial data output, with a processor, which has a parallel data input, the coupling device, comprising:

a serial data interface configured to receive data;

a parallel data interface configured to transmit data;

a cache memory coupled to the serial data interface and to the parallel data interface, wherein the cache memory is configured to receive and store data, which have been received in a serial data format via the serial data interface, to transmit data stored in the cache memory to the parallel data interface; and

a buffer memory, which is coupled with the serial data interface and with the parallel data interface, wherein the buffer memory is configured to store data, which the serial data interface has received, and to output data which are stored in the buffer memory, to the parallel data interface, and

a processor having a parallel data interface, which is coupled with the parallel data interface of the coupling device.

13. The processor arrangement of claim 12 ,

wherein the processor is a processor of a communication terminal device.

14. The processor arrangement of claim 13 ,

wherein the processor is a processor of a mobile radio telephone.

15. The processor arrangement of claim 12 ,

being comprised in an integrated circuit.

16. A data processing arrangement, comprising:

a coupling device for coupling a memory, which has a serial data output, with a processor, which has a parallel data input, the coupling device, comprising:

a serial data interface configured to receive data;

a parallel data interface configured to transmit data; and

a cache memory coupled to the serial data interface and to the parallel data interface, wherein the cache memory is configured to receive and store data, which have been received in a serial data format via the serial data interface, and to transmit data stored in the cache memory to the parallel data interface,

wherein the cache memory is further configured to check as to whether data, which are requested by means of instruction data received by means of the parallel data interface, are stored in the cache memory, and, in case that the requested data are stored in the cache memory, to directly output the stored data to the parallel data interface, and, in case that the requested data are not stored in the cache memory, to cause the serial data interface to transmit instruction data, which specify that the requested data should be read from a memory and should be received by the serial data interface;

a processor having a parallel data interface, which is coupled with the parallel data interface of the coupling device; and

a memory having a serial data interface, which is coupled with the serial data interface of the coupling device.

17. The data processing arrangement of claim 16 ,

wherein the memory is a serial Flash memory.

18. The data processing arrangement of claim 16 ,

which is implemented in form circuits on a common substrate.

19. A method for transmitting data from a memory, which has a serial data output, to a processor, which has a parallel data input, the method comprising:

transmitting data from the memory to a cache memory in serial data format;

receiving and storing the data, which have been received in a serial data format, in the cache memory;

reading the stored data from the cache memory;

transmitting the read data in a parallel data format to the processor; and

storing data, which has been received in serial format, in a buffer memory, and outputting data, which are stored in the buffer memory, in a parallel data format.

20. The method of claim 19 ,

wherein the data are requested by the processor.

21. The method of claim 20 , further comprising:

checking as to whether the data requested by the processor are stored in the cache memory;

in case that the requested data are stored in the cache memory, reading the data from the cache memory and directly transmitting the read data to the processor; and

in case that the requested data are not stored in the cache memory, requesting the data from the memory.

22. The method of claim 19 ,

wherein the requested data comprise instruction code which should directly be executed by the processor.