Simultaneous speculative threading light mode
A system and method for management of resource allocation of threads for efficient execution of instructions. Prior to dispatching decoded instructions of a first thread from the instruction fetch unit to a buffer within a scheduler, logic within the instruction fetch unit may determine the buffer is already full of dispatched instructions. However, the logic may also determine that a buffer for a second thread within the core or micro core is available. The second buffer may receive and issue decoded instructions for the first thread until the buffer is becomes unavailable. While the second buffer receives and issues instructions for the first thread, the throughput of the system for the first thread may increase due to a reduction in wait cycles.
1. A system comprising:
a scheduler comprising a first buffer including a first plurality of entries allocated for use by a first thread and a second buffer including a second plurality of entries allocated for use by a second thread;
an execution unit; and
an instruction fetch unit, wherein the instruction fetch unit is configured to:
identify a state associated with buffers in the scheduler;
dispatch decoded instructions of the first thread to the first buffer, in response to detecting the state indicates a non-combined state; and
temporarily dispatch decoded instructions of the first thread to the second buffer as long as the first thread is assigned by an operating system to receive instructions and the state indicates a combined state, wherein the state indicates the combined state responsive to detecting:
there is no available entry of the first plurality of entries in the first buffer;
there is an available entry of the second plurality of entries in the second buffer; and
the second thread is not assigned by an operating system to receive instructions.
2. The system as recited in claim 1 , wherein in response to detecting the state identifies the combined state, the instruction fetch unit is further configured to set an index which indicates dispatched instructions of the first thread are to be conveyed to the second buffer.
3. The system as recited in claim 1 , wherein the scheduler further comprises a third buffer including a third plurality of entries allocated for use by a third thread and the instruction fetch unit is further configured to:
determine there is no available entry of the third plurality of entries in the third buffer; and
determine the third thread waits for instruction dispatch due to at least one of the following: the first thread began prior to the third thread, the first thread has a higher associated priority than the third thread, and the first thread is chosen by a round-robin scheme.
4. The system as recited in claim 1 , wherein the instruction fetch unit is further configured to: detect a buffer within the scheduler is unavailable when the buffer is in an active state and is full.
5. The system as recited in claim 4 , wherein the active state comprises a state wherein a thread is assigned by an operating system to receive instructions.
6. The system as recited in claim 1 , wherein the scheduler is configured to:
mark instructions according to a thread of a given instruction; and
issue stored instructions from a buffer to the execution unit.
7. The system as recited in claim 6 , wherein the scheduler does not mark stored instructions according to a buffer storing the stored instructions.
8. A method comprising:
allocating a first buffer including a first plurality of entries for use by a first thread, and a second buffer including a second plurality of entries for use by a second thread;
identifying a state associated with buffers in a scheduler;
fetching instructions corresponding to a plurality of threads; and
dispatching the instructions to the scheduler, wherein said dispatching comprises:
dispatching decoded instructions of the first thread to the first buffer, in response to detecting the state identifies a non-combined state; and
temporarily dispatching decoded instructions of the first thread to the second buffer as long as the first thread is assigned by an operating system to receive instructions and the state indicates a combined state, wherein the state indicates the combined state responsive to detecting:
there is no available entry of the first plurality of entries in the first buffer;
there is an available entry of the second plurality of entries in the second buffer; and
the second thread is not assigned by an operating system to receive instructions.
9. The method as recited in claim 8 , wherein in response to detecting the state identifies the combined state, the instruction fetch unit is further configured to set an index which indicates dispatched instructions of the first thread are to be conveyed to the second buffer.
10. The method as recited in claim 8 , further comprising:
allocating a third buffer including a third plurality of entries for use by a third thread;
determining there is no available entry of the third plurality of entries in the third buffer; and
determining the third thread waits for instruction dispatch due to at least one of the following: the first thread began prior to the third thread, the first thread has a higher associated priority than the third thread, and the first thread is chosen by a round-robin scheme.
11. The method as recited in claim 8 , further comprising detecting a buffer is unavailable when the buffer is in an active state and is full of dispatched instructions.
12. The method as recited in claim 8 , further comprising:
marking instructions according to a thread of a given instruction; and
issuing stored instructions from a buffer to the execution unit.
13. The method as recited in claim 11 , further comprising the active state comprises a thread is assigned by an operating system to receive instructions.
14. The method as recited in claim 12 further comprising not marking stored instructions according to a buffer storing the stored instructions.
15. A fetch buffer control unit comprising:
an interface configured to communicate with a first buffer including a first plurality of entries allocated for use by a first thread and a second buffer including a second plurality of entries allocated for use by a second thread, a decoder unit, and a scheduler; and
circuitry configured to:
indicate when to dispatch decoded instructions to the scheduler;
identify a state associated with buffers in the scheduler;
convey a number of decoded instructions to dispatch to the scheduler;
provide an index pointing to a buffer within the scheduler; and
detecting the state identifies a combined state, wherein said detecting comprises:
there is no available entry of the first plurality of entries in the first buffer;
there is an available entry of the second plurality of entries in the second buffer; and
the second thread is not assigned by an operating system to receive instructions;
temporarily set the index to point to the second buffer as long as the first thread is assigned by an operating system to receive instructions and the state indicates a combined state when notifying to dispatch instructions of the first thread; and
set the index to point to the first buffer when notifying to dispatch instructions of the first thread, in response detecting the state identifies a non-combined state.
16. The fetch buffer control unit as recited in claim 15 , wherein the fetch buffer control unit is further configured to detect a buffer within the scheduler is unavailable when the buffer is in an active state and is full of dispatched instructions.
17. The fetch buffer control unit as recited in claim 16 , wherein the active state comprises a state wherein a thread is assigned by an operating system to receive instructions.