METHODS OF COMMUNICATING TO, MEMORY MODULES IN A MEMORY CHANNEL

1 - 15 . (canceled)

16 . A method of communicating to different types of memory modules in a memory channel, the method comprising:

initializing a programmable heterogeneous memory controller to each memory module coupled to a memory channel bus;

adapting each pin of a memory channel interface to communicate over wire interconnect of the memory channel bus to respective pins of each memory module in response to each different type of memory module being accessed;

generating logic signals for communication over the wire interconnect of the memory channel bus to each memory module in response to each different type of memory module being accessed; and

wherein the logic signals are generated on the wire interconnect of the memory channel bus with appropriate signal timing to communicate with each memory module in response to each different type of memory module being accessed.

17 . The method of claim 16 , further comprising:

loading into the heterogeneous memory controller one or more memory module software drivers associated with the type of memory modules being accessed.

18 . The method of claim 17 , further comprising:

downloading at least one of the one or more memory module software drivers over a network.

19 . The method of claim 17 , wherein

in response to each different type of memory module being accessed, the one or more memory module software drivers each include information regarding the respective pins of the memory module, logic signals to communicate with the memory module, and signal timing to communicate with the memory module.

20 . The method of claim 16 , wherein the adapting of each pin includes

assigning additional functionality to underused or unused pins so that a communication protocol between one or more memory modules and the programmable heterogeneous memory controller may be extended.

21 . The method of claim 20 , wherein

address and control signal lines are used in a different manner to address additional memory to increase memory capacity.

22 . The method of claim 20 , wherein

pre-existing address pins are used over multiple cycles to form a larger address to address additional memory and increase memory capacity.

23 . The method of claim 20 , wherein

a feedback pin is defined so that the programmable heterogeneous memory controller can receive status information from the memory module.

24 . The method of claim 16 , wherein

the generating of logic signals includes

generating active high logic signals or active low logic signals in response to the type of memory module being accessed.

25 . The method of claim 16 , wherein

the initializing of the programmable heterogeneous memory controller includes

polling each socket in the memory channel for a memory module;

reading a memory module identification from each memory module to determine the type of memory module coupled into each socket; and

loading a memory module software driver into the programmable heterogeneous memory controller for each different type of memory module coupled into the memory channel.

26 . The method of claim 25 , wherein

the initializing of the programmable heterogeneous memory controller further includes

storing each memory module identifier associated with each socket into the programmable heterogeneous memory controller.

27 . The method of claim 26 , wherein

the initializing of the programmable heterogeneous memory controller further includes

loading a state machine with the memory module software driver to access the memory module in a given socket.

28 . A method of communicating with a non-volatile memory module in a memory channel, the method comprising:

signaling to a non-volatile memory module to perform an operation;

signaling back to a memory controller using a feedback status control signal to indicate that the non-volatile memory module is busy;

waiting for the non-volatile memory module to finish the operation after the feedback status control signal indicates the non-volatile memory module is busy; and

signaling back to the memory controller using the feedback status control signal to indicate that the non-volatile memory module is now ready to perform another operation.

29 . The method of claim 28 , wherein

the operation the non-volatile memory module is signaled to perform is to erase a sector of non-volatile memory.

30 . The method of claim 28 , wherein

the operation the non-volatile memory module is signaled to perform is to write a word or words of data into non-volatile memory.

31 . The method of claim 28 , wherein

the feedback status control signal from the non-volatile memory module is coupled into the memory controller over a point-to-point wire interconnect in the memory channel bus.

32 . The method of claim 28 , further comprising:

performing the operation into a first bank of non-volatile memory in the non-volatile memory module; and

concurrently performing a read operation into a second bank of non-volatile memory in the non-volatile memory module while the operation is pending in the first bank of non-volatile memory.

33 . The method of claim 28 , wherein

the another operation is initiated by the memory controller to erase a sector of non-volatile memory in the non-volatile memory module.

34 . The method of claim 28 , wherein

the another operation is initiated by the memory controller to write a word of data into non-volatile memory in the non-volatile memory module.

35 . The method of claim 28 , further comprising:

interrupting a processor to signal that the non-volatile memory module is ready for another operation.

36 - 59 . (canceled)