Display panel with TFT and gate line disposed between sub-electrodes of pixel electrode
View Patent ↗A display panel includes gate lines formed on a substrate, storage electrode lines formed on the substrate and being parallel to the gate lines, data lines insulated from the gate lines and crossing the gate lines, a plurality of thin film transistors (TFTs) connected with the gate lines and the data lines, and pixel electrodes having a first sub-electrode connected with a TFT and a second sub-electrode formed at a side opposite the first sub-electrode with respect to a gate line, wherein the TFT and a storage electrode line are disposed between the first and second sub-electrodes.
1. A display panel comprising:
a gate line disposed on a substrate;
a storage electrode line disposed on the substrate parallel to the gate line;
a data line insulated from the gate line and crossing the gate line;
a thin film transistor connected with the gate line and the data line; and
a pixel electrode having a first sub-electrode connected with the thin film transistor and a second sub-electrode disposed at a side opposite the first sub-electrode with respect to the gate line,
wherein the thin film transistor, the gate line, and the storage electrode line are disposed between the first sub-electrode and the second sub-electrode.
2. The display panel of claim 1 , further comprising:
a counter substrate facing the substrate;
a color filter disposed on the counter substrate; and
a common electrode disposed on the color filter and having a plurality of cutout portions.
3. The display panel of claim 2 , wherein the thin film transistor comprises:
a gate electrode connected with the gate line;
a semiconductor insulated from the gate electrode and overlapping the gate electrode;
a source electrode connected with the data line and overlapping the semiconductor; and
a drain electrode overlapping the semiconductor and facing the source electrode.
4. The display panel of claim 3 , wherein a capacitor is formed by the drain electrode overlapping the storage electrode line.
5. The display panel of claim 3 , further comprising
a connecting member that connects the first sub-electrode and the second sub-electrode.
6. The display panel of claim 5 , wherein the connecting member comprises a protrusion electrically connected with the drain electrode.
7. The display panel of claim 2 , wherein the thin film transistor respectively comprises:
a semiconductor formed on the substrate and comprising a channel region and a drain region and a source region;
a gate electrode insulated from the channel region and overlapping the channel region;
a source electrode electrically connected with the source region; and
a drain electrode electrically connected with the drain region.
8. The display panel of claim 7 , wherein the semiconductor includes polycrystalline silicon.
9. The display panel of claim 7 , wherein the storage electrode line comprises an expanded portion, and the semiconductor further comprises a storage capacitor region overlapping the expanded portion.
10. The display panel of claim 7 , wherein a capacitor is formed by the drain electrode overlapping the storage electrode line.
11. The display panel of claim 7 , wherein a connecting member includes a protrusion electrically connected with the drain electrode.
12. The display panel of claim 2 , further comprising an auxiliary electrode formed on the substrate and extending parallel to the gate line.
13. The display panel of claim 12 , wherein a boundary line of the auxiliary electrode coincides with an upper boundary line or a lower boundary line of a pixel electrode of adjacent pixel electrodes.
14. The display panel of claim 12 , wherein a boundary line of the auxiliary electrode lies between the upper boundary line and the lower boundary line of adjacent pixel electrodes.
15. The display panel of claim 12 , wherein the same voltage is applied to the auxiliary electrode and a common electrode.
16. The display panel of claim 12 , wherein the gate line and the auxiliary electrode are made of the same material.
17. The display panel of claim 2 , wherein the storage electrode line is positioned on a boundary line between adjacent pixel electrodes.
18. The display panel of claim 17 , wherein the storage electrode line further includes a storage electrode that protrudes toward thin film transistor.
19. The display panel of claim 18 , wherein the thin film transistor further comprises:
agate electrode connected with the gate line;
a semiconductor insulated from and overlapping the gate electrode;
a source electrode connected with the data line and overlapping the semiconductor; and
a drain electrode overlapping the semiconductor and facing the source electrode,
wherein the drain electrode is connected with a capacitor conductor overlapping the storage electrode.
20. The display panel of claim 18 , wherein the storage electrode is up -and-down and right-and-left symmetrically formed with respect to the cut-out portion.
21. The display panel of claim 2 , wherein the cutout portions are disposed at positions corresponding to a center of the first sub-electrode and a center of the second sub-electrode.
22. The display panel of claim 21 , wherein the cutout portions have a quadrangle shape with rounded corners or a round shape.
23. The display panel of claim 2 , further comprising a light blocking member formed on the counter substrate and disposed between the first sub-electrode and the second sub-electrode.
24. The display panel of claim 1 , wherein the first sub-electrode and the second sub-electrodes have a quadrangle shape with rounded corners.