Method and system for designing test circuit in a system on chip
View Patent ↗A method and system for designing a test circuit in a System on Chip (SOC) includes identifying the test design constraints of the test circuit. The SOC is partitioned logically into a first set of logic blocks and a second set of logic blocks. A first set of scan chains is inserted in the first set of logic blocks, and a second set of scan chains is inserted in the second set of logic blocks, based on the test design constraints. Bypass circuits are inserted in the paths of the second set of scan chains, which are capable of bypassing at least one logic block of the second set of logic blocks during testing of the SOC.
1. A method for designing a test circuit in a System on Chip (SOC) design using a system for designing a test circuit, wherein the system includes a constraint identifier, an SOC partitioning module, and a scan chain construction module, and wherein the SOC design includes a plurality of logic blocks, the method comprising:
identifying test design constraints for the test circuit with the constraint identifier, wherein the test design constraints include a number of scan chains and an average length of a scan chain;
logically partitioning the SOC design into at least a first set of logic blocks and a second set of logic blocks with the SOC partitioning module, wherein the first set of logic blocks includes design logic specific to basic features of the SOC design and the second set of logic blocks includes application specific logic of the SOC design;
inserting a first set of scan chains in the first set of logic blocks and a second set of scan chains in the second set of logic blocks with the scan chain construction module, based on the test design constraints;
inserting a plurality of bypass circuits in a path of at least one scan chain of the second set of scan chains with the scan chain construction module, wherein each of the bypass circuits is capable of bypassing at least one logic block of the second set of logic blocks during testing of the SOC design; and
further comprising partitioning the second set of logic blocks into at least one subset of logic blocks based on a target application of each logic block of the second set of logic blocks prior to inserting the second set of scan chains.
2. The method for designing the test circuit in the SOC design of claim 1 , wherein identifying the test design constraints is based on a number of input and output pins of the SOC design.
3. The method for designing the test circuit in the SOC design of claim 1 , wherein identifying the test design constraints is based on a number of channels in an Automatic Test Equipment (ATE) used in testing of the SOC design.
4. A system for designing a test circuit in a System on Chip (SOC) design, the SOC design including a plurality of logic blocks, the system comprising:
a constraints identifier connected to the scan chain construction module that identifies test design constraints, wherein the test design constraints are a number of scan chains and an average length of a scan chain;
an SOC partitioning module that partitions the SOC design logically into a first set of logic blocks and a second set of logic blocks, wherein the first set of logic blocks includes design logic specific to basic features of the SOC design and the second set of logic blocks includes application specific logic of the SOC design, and further partitions the second set of logic blocks into at least one subset of logic blocks; and
a scan chain construction module connected to the SOC partitioning module that inserts a first set of scan chains in the first set of logic blocks and a second set of scan chains in the second set of logic blocks, based on the test design constraints, and inserts a plurality of bypass circuits in the second set of logic blocks.
5. The system for designing the test circuit in a SOC design of claim 4 , wherein the test design constraints are based on a number of input and output pins of the SOC design.
6. The system for designing the test circuit in the SOC design of claim 4 , wherein the test design constraints are based on a number of channels in the Automatic Test Equipments (ATE) used in testing of the SOC design.
7. The system for designing the test circuit in the SOC design of claim 4 , wherein each of the plurality of bypass circuits is capable of bypassing at least one logic block of the second set of logic blocks.
8. The system for designing the test circuit in the SOC design of claim 4 , wherein each of the plurality of bypass circuits includes a multiplexer.
9. A computer program product stored on a computer storage device and operable on a computer system for designing a test circuit in a system on chip (SOC) design, the SOC design including a plurality of logic blocks, the computer program product comprising:
a first set of program instructions executed by the computer system that identifies test design constraints for the test circuit, wherein the test design constraints are a number of scan chains and an average length of a scan chain;
a second set of program instructions executed by the computer system that partitions the SOC design logically into at least a first set of logic blocks and a second set of logic blocks, wherein the first set of logic blocks includes design logic representing basic features of the SOC design and the second set of logic blocks includes application specific logic of the SOC design;
a third set of program instructions executed by the computer system that inserts a first set of scan chains in the first set of logic blocks and a second set of scan chains in the second set of logic blocks; and
a fourth set of program instructions executed by the computer system that inserts a plurality of bypass circuits in the second set of logic blocks, wherein each of the plurality of bypass circuits is capable of bypassing at least one logic block of the second set of logic blocks during testing of the SOC design; and
wherein the second set of program instructions that partitions the SOC design comprises a fifth set of program instructions that partitions the second set of logic blocks into at least one subset of logic blocks based on a target application of each logic block of the second set of logic blocks.