Fabrication of CCD image sensors using single layer polysilicon

1. A method for fabricating CCD imaging structures comprising the steps of;

providing a silicon substrate;

growing a dielectric layer overlying the silicon substrate;

depositing a first layer of polysilicon overlying the dielectric layer;

removing at least a portion of the first layer of polysilicon to form a plurality of polysilicon gates and first predetermined inter-gate gaps, each of plurality of the polysilicon gates having a predetermined line width;

depositing a second layer of polysilicon of a predetermined thickness overlying the plurality of polysilicon gates and the first predetermined inter-gate gaps; and

removing at least a portion of the second layer of polysilicon from between gates of the plurality of polysilicon gates to define a plurality of non-overlapping polysilicon gates and second predetermined inter-gate gaps that expose the dielectric layer, the second predetermined inter-gate gaps being smaller than the first predetermined inter-gate gaps.

2. The method of claim 1 , wherein the step of removing at least a portion of the first layer of polysilicon to form a plurality of polysilicon gates and first predetermined inter-gate gaps further comprises the steps of:

applying photolithography to the first layer of polysilicon to form a desired gate pattern; and

anisotropically etching the first layer of polysilicon to remove at least a portion of the first layer of polysilicon to form the polysilicon gates and the first predetermined inter-gate gaps.

3. The method of claim 2 , wherein the step of removing at least a portion of the second layer of polysilicon from between gates of the plurality of polysilicon gates further comprises the step of anisotropically etching the second layer of polysilicon to define the plurality of non-overlapping polysilicon gates and second predetermined inter-gate gaps.

4. The method of claim 3 , further comprising the step of doping the second layer of polysilicon and the first layer of polysilicon.

5. The method of claim 4 , wherein the second layer of polysilicon and the first layer of polysilicon are doped with one of n type and p type dopants.

6. The method of claim 4 , wherein the second layer of polysilicon and the first layer of polysilicon are doped via diffusion.

7. The method of claim 4 , wherein the second layer of polysilicon and the first layer of polysilicon are doped via ion implantation.

8. The method of claim 4 , further comprising the step of siliciding the non-overlapping polysilicon gates to increase conductivity.

9. The method of claim 1 , further comprising the step of depositing a dielectric layer overlying the non-overlapping polysilicon gates and exposed dielectric layer.

10. The method of claim 9 , wherein the dielectric layer overlying the silicon substrate and the dielectric layer overlying the non-overlapping polysilicon gates are made of silicon dioxide.

11. The method of claim 1 , wherein the width of each of the second predetermined inter-gate gaps is about 0.2 um.

12. The method of claim 11 , wherein the width of each of the first predetermined inter-gale gaps is between about 0.3 um and 2.3 um.

13. The method of claim 12 , wherein the predetermined line width of each of the polysilicon gates is between about 0.5 um and about 12 um.

14. A method for fabricating CCD imaging structures, comprising the steps of:

providing a silicon substrate;

growing a dielectric layer overlying the silicon substrate;

depositing a first layer of a conductive material overlying the dielectric layer;

removing at least a portion of the first layer of conductive material to form a plurality of conductive gates and first predetermined inter-gate gaps, each of plurality of the conductive gates having a predetermined line width;

depositing a second layer of the conductive material of a predetermined thickness overlying the plurality of conductive gates and the first inter-gate gaps; and

removing at least a portion of the second layer of conductive material from between gates of the plurality of conductive gates to define a plurality of non-overlapping conductive gates and second predetermined inter-gate gaps that expose the dielectric layer, the second predetermined inter-gate gaps being smaller than the first predetermined inter-gate gaps.

15. The method of claim 14 , wherein the conductive material is metal.

16. The method of claim 14 , wherein the step of removing at least a portion of the first layer of conductive material to form a plurality of conductive gates and first inter-gate gaps further comprises the steps of:

applying photolithography to the first layer of conductive material to form a desired gate pattern; and

anisotropically etching the first layer of conductive material to remove at least a portion of the first layer of conductive material to form the conductive gates and the first predetermined inter-gate gaps.

17. The method of claim 16 , wherein the step of removing at least a portion of the second layer of conductive material from between gates of the plurality of conductive gates further comprises the step of anisotropically etching the second layer of conductive material to define the plurality of non-overlapping conductive gates and second predetermined inter-gate gaps.